@inproceedings{b1f3783ec39c48428c0443264df1cd50,
title = "A 19 fJ/op, Low-Offset StrongARM Latch Comparator for Low-Power High-Speed Applications",
abstract = "In this paper, a new StrongARM latch comparator design has been proposed for low-power high-speed applications. The proposed design improves the energy consumption and propagation delay when compared to the previous designs in the literature. The proposed design is post-layout simulated in TSMC 65 nm technology node and it achieves a low energy consumption of 19.31 fJ per operation and a low propagation delay of 211 ps. Moreover, the proposed design shows a highly favorable input offset voltage of 0.56 mV and achieves a maximum frequency of 8 GHz. Furthermore, the proposed design reduced the transistor stack that allows it to be used in the low-voltage supply application.",
keywords = "CMOS latch, forward body biasing, high-speed circuit, low-power circuit, offset voltage, StrongARM latch comparator",
author = "Abdullah Alshehri and Khaled Salama and Hossein Fariborzi",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 ; Conference date: 19-05-2024 Through 22-05-2024",
year = "2024",
doi = "10.1109/ISCAS58744.2024.10557840",
language = "English (US)",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2024 - IEEE International Symposium on Circuits and Systems",
address = "United States",
}
