TY - GEN
T1 - A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation
AU - Omran, Hesham
AU - Alhoshany, Abdulaziz
AU - Alahmadi, Hamzah
AU - Salama, Khaled N.
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2016/10/6
Y1 - 2016/10/6
N2 - We propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area. © 2016 IEEE.
AB - We propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area. © 2016 IEEE.
UR - http://hdl.handle.net/10754/622500
UR - http://ieeexplore.ieee.org/document/7573533/
UR - http://www.scopus.com/inward/record.url?scp=84990960992&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2016.7573533
DO - 10.1109/VLSIC.2016.7573533
M3 - Conference contribution
SN - 9781509006359
BT - 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
