A best-first soft/hard decision tree searching MIMO decoder for a 4 × 4 64-QAM system

Chungan Shen; Ahmed M. Eltawil; Khaled N. Salama; Sudip Mondal

doi:10.1109/TVLSI.2011.2159821

A best-first soft/hard decision tree searching MIMO decoder for a 4 × 4 64-QAM system

Chungan Shen, Ahmed M. Eltawil, Khaled N. Salama, Sudip Mondal

Research output: Contribution to journal › Article › peer-review

25 Scopus citations

Abstract

This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER performance. The proposed multiple-input-multiple-output decoder supports a 4 × 4 64-QAM system and was synthesized with 65-nm CMOS technology at 333 MHz clock frequency. For the hard output scheme the design can achieve an average throughput of 257.8 Mbps at 24 dB signal-to-noise ratio (SNR) with area equivalent to 54.2 Kgates and a power consumption of 7.26 mW. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW. © 2011 IEEE.

Original language	English (US)
Pages (from-to)	1537-1541
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	8
DOIs	https://doi.org/10.1109/TVLSI.2011.2159821
State	Published - Aug 2012

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

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10.1109/TVLSI.2011.2159821

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@article{b35b3cfd1a4844809dce05a0d1754112,

title = "A best-first soft/hard decision tree searching MIMO decoder for a 4 × 4 64-QAM system",

abstract = "This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER performance. The proposed multiple-input-multiple-output decoder supports a 4 × 4 64-QAM system and was synthesized with 65-nm CMOS technology at 333 MHz clock frequency. For the hard output scheme the design can achieve an average throughput of 257.8 Mbps at 24 dB signal-to-noise ratio (SNR) with area equivalent to 54.2 Kgates and a power consumption of 7.26 mW. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW. {\textcopyright} 2011 IEEE.",

author = "Chungan Shen and Eltawil, {Ahmed M.} and Salama, {Khaled N.} and Sudip Mondal",

note = "KAUST Repository Item: Exported on 2020-10-01 Acknowledgements: Manuscript received September 17, 2010; revised January 13, 2011 and April 14, 2011; accepted May 22, 2011. Date of publication July 18, 2011; date of current version June 14, 2012. This work was supported in part by the Department of Justice, National Institute of Justice DOJ/NIJ under grant 2006-IJ-CX-K044.",

year = "2012",

month = aug,

doi = "10.1109/TVLSI.2011.2159821",

language = "English (US)",

volume = "20",

pages = "1537--1541",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - A best-first soft/hard decision tree searching MIMO decoder for a 4 × 4 64-QAM system

AU - Shen, Chungan

AU - Eltawil, Ahmed M.

AU - Salama, Khaled N.

AU - Mondal, Sudip

N1 - KAUST Repository Item: Exported on 2020-10-01 Acknowledgements: Manuscript received September 17, 2010; revised January 13, 2011 and April 14, 2011; accepted May 22, 2011. Date of publication July 18, 2011; date of current version June 14, 2012. This work was supported in part by the Department of Justice, National Institute of Justice DOJ/NIJ under grant 2006-IJ-CX-K044.

PY - 2012/8

Y1 - 2012/8

N2 - This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER performance. The proposed multiple-input-multiple-output decoder supports a 4 × 4 64-QAM system and was synthesized with 65-nm CMOS technology at 333 MHz clock frequency. For the hard output scheme the design can achieve an average throughput of 257.8 Mbps at 24 dB signal-to-noise ratio (SNR) with area equivalent to 54.2 Kgates and a power consumption of 7.26 mW. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW. © 2011 IEEE.

AB - This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER performance. The proposed multiple-input-multiple-output decoder supports a 4 × 4 64-QAM system and was synthesized with 65-nm CMOS technology at 333 MHz clock frequency. For the hard output scheme the design can achieve an average throughput of 257.8 Mbps at 24 dB signal-to-noise ratio (SNR) with area equivalent to 54.2 Kgates and a power consumption of 7.26 mW. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW. © 2011 IEEE.

UR - http://hdl.handle.net/10754/562259

UR - http://ieeexplore.ieee.org/document/5955092/

UR - http://www.scopus.com/inward/record.url?scp=84862705927&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2011.2159821

DO - 10.1109/TVLSI.2011.2159821

M3 - Article

SN - 1063-8210

VL - 20

SP - 1537

EP - 1541

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 8

ER -

A best-first soft/hard decision tree searching MIMO decoder for a 4 × 4 64-QAM system

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