A class of low power error compensation iterative decoders

Amr M.A. Hussien; Muhammad S. Khairy; Amin Khajeh; Ahmed M. Eltawil; Fadi J. Kurdahi

doi:10.1109/GLOCOM.2011.6134075

A class of low power error compensation iterative decoders

Amr M.A. Hussien, Muhammad S. Khairy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders. © 2011 IEEE.

Original language	English (US)
Title of host publication	GLOBECOM - IEEE Global Telecommunications Conference
DOIs	https://doi.org/10.1109/GLOCOM.2011.6134075
State	Published - Dec 1 2011
Externally published	Yes

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10.1109/GLOCOM.2011.6134075

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title = "A class of low power error compensation iterative decoders",

abstract = "Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders. {\textcopyright} 2011 IEEE.",

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AU - Khajeh, Amin

AU - Eltawil, Ahmed M.

AU - Kurdahi, Fadi J.

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Y1 - 2011/12/1

N2 - Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders. © 2011 IEEE.

AB - Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders. © 2011 IEEE.

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SN - 9781424492688

BT - GLOBECOM - IEEE Global Telecommunications Conference

ER -

A class of low power error compensation iterative decoders

Abstract

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