A design of low-power 10-bit 1-MS/s asynchronous SAR ADC for DSRC application

Deeksha Verma, Khuram Shehzad, Danial Khan, Sung Jin Kim, Young Gun Pu, Sang Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Kang Yoon Lee

Research output: Contribution to journalArticlepeer-review

16 Scopus citations


A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.
Original languageEnglish (US)
Pages (from-to)1-11
Number of pages11
JournalElectronics (Switzerland)
Issue number7
StatePublished - Jul 1 2020
Externally publishedYes


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