A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer

B. Hornung; R. Khamankar; H. Niimi; M. Goodwin; L. Robertson; D. Miles; B. Kirkpatrick; H. AlShareef; A. Varghese; M. Bevan; P. Nicollian; P. R. Chidambaram; S. Chakravarthi; A. Gurba; X. Zhang; J. Blatchford; B. Smith; J. P. Lu; J. Deloach; B. Rathsack; C. Bowen; G. Thakar; C. Machala; T. Grider

doi:10.1109/vlsit.2003.1221098

A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer

B. Hornung^*, R. Khamankar, H. Niimi, M. Goodwin, L. Robertson, D. Miles, B. Kirkpatrick, H. AlShareef, A. Varghese, M. Bevan, P. Nicollian, P. R. Chidambaram, S. Chakravarthi, A. Gurba, X. Zhang, J. Blatchford, B. Smith, J. P. Lu, J. Deloach, B. RathsackC. Bowen, G. Thakar, C. Machala, T. Grider

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

A 90nm logic technology is presented featuring an aggressively scaled 37nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5V IO transistor with lOOnm gate length and dual plasma nitrided gate dielectric.

Original language	English (US)
Pages (from-to)	85-86
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/vlsit.2003.1221098
State	Published - 2003
Externally published	Yes
Event	2003 Symposium on VLSI Technology - Kyoto, Japan Duration: Jun 10 2003 → Jun 12 2003

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/vlsit.2003.1221098

Cite this

Hornung, B., Khamankar, R., Niimi, H., Goodwin, M., Robertson, L., Miles, D., Kirkpatrick, B., AlShareef, H., Varghese, A., Bevan, M., Nicollian, P., Chidambaram, P. R., Chakravarthi, S., Gurba, A., Zhang, X., Blatchford, J., Smith, B., Lu, J. P., Deloach, J., ... Grider, T. (2003). A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer. Digest of Technical Papers - Symposium on VLSI Technology, 85-86. https://doi.org/10.1109/vlsit.2003.1221098

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title = "A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer",

abstract = "A 90nm logic technology is presented featuring an aggressively scaled 37nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5V IO transistor with lOOnm gate length and dual plasma nitrided gate dielectric.",

author = "B. Hornung and R. Khamankar and H. Niimi and M. Goodwin and L. Robertson and D. Miles and B. Kirkpatrick and H. AlShareef and A. Varghese and M. Bevan and P. Nicollian and Chidambaram, {P. R.} and S. Chakravarthi and A. Gurba and X. Zhang and J. Blatchford and B. Smith and Lu, {J. P.} and J. Deloach and B. Rathsack and C. Bowen and G. Thakar and C. Machala and T. Grider",

year = "2003",

doi = "10.1109/vlsit.2003.1221098",

language = "English (US)",

pages = "85--86",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2003 Symposium on VLSI Technology ; Conference date: 10-06-2003 Through 12-06-2003",

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Hornung, B, Khamankar, R, Niimi, H, Goodwin, M, Robertson, L, Miles, D, Kirkpatrick, B, AlShareef, H, Varghese, A, Bevan, M, Nicollian, P, Chidambaram, PR, Chakravarthi, S, Gurba, A, Zhang, X, Blatchford, J, Smith, B, Lu, JP, Deloach, J, Rathsack, B, Bowen, C, Thakar, G, Machala, C & Grider, T 2003, 'A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer', Digest of Technical Papers - Symposium on VLSI Technology, pp. 85-86. https://doi.org/10.1109/vlsit.2003.1221098

TY - JOUR

T1 - A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer

AU - Hornung, B.

AU - Khamankar, R.

AU - Niimi, H.

AU - Goodwin, M.

AU - Robertson, L.

AU - Miles, D.

AU - Kirkpatrick, B.

AU - AlShareef, H.

AU - Varghese, A.

AU - Bevan, M.

AU - Nicollian, P.

AU - Chidambaram, P. R.

AU - Chakravarthi, S.

AU - Gurba, A.

AU - Zhang, X.

AU - Blatchford, J.

AU - Smith, B.

AU - Lu, J. P.

AU - Deloach, J.

AU - Rathsack, B.

AU - Bowen, C.

AU - Thakar, G.

AU - Machala, C.

AU - Grider, T.

PY - 2003

Y1 - 2003

N2 - A 90nm logic technology is presented featuring an aggressively scaled 37nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5V IO transistor with lOOnm gate length and dual plasma nitrided gate dielectric.

AB - A 90nm logic technology is presented featuring an aggressively scaled 37nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5V IO transistor with lOOnm gate length and dual plasma nitrided gate dielectric.

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U2 - 10.1109/vlsit.2003.1221098

DO - 10.1109/vlsit.2003.1221098

M3 - Conference article

AN - SCOPUS:0141761546

SN - 0743-1562

SP - 85

EP - 86

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2003 Symposium on VLSI Technology

Y2 - 10 June 2003 through 12 June 2003

ER -

A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer

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