TY - GEN
T1 - A High Speed Dynamic StrongARM Latch Comparator
AU - Al-Qadasi, Mohammed
AU - Alshehri, Abdullah
AU - Almansouri, Abdullah Saud Mohammed
AU - Al Attar, Talal
AU - Fariborzi, Hossein
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2019/2/28
Y1 - 2019/2/28
N2 - In this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional [4] and improved StrongARM [5], respectively, while the energy consumption has also been reduced.
AB - In this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional [4] and improved StrongARM [5], respectively, while the energy consumption has also been reduced.
UR - http://hdl.handle.net/10754/631285
UR - https://ieeexplore.ieee.org/document/8624100
UR - http://www.scopus.com/inward/record.url?scp=85062229570&partnerID=8YFLogxK
U2 - 10.1109/mwscas.2018.8624100
DO - 10.1109/mwscas.2018.8624100
M3 - Conference contribution
SN - 9781538673928
SP - 540
EP - 541
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
