A macro-model for the efficient simulation of an ADC-based RNG

Fabio Pareschi; Gianluca Setti; Riccardo Rovatti

doi:10.1109/ISCAS.2005.1465594

A macro-model for the efficient simulation of an ADC-based RNG

Fabio Pareschi, Gianluca Setti, Riccardo Rovatti

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Pages	4349-4352
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2005.1465594
State	Published - Dec 1 2005
Externally published	Yes

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10.1109/ISCAS.2005.1465594

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title = "A macro-model for the efficient simulation of an ADC-based RNG",

abstract = "In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. {\textcopyright} 2005 IEEE.",

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N2 - In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE.

AB - In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE.

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M3 - Conference contribution

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EP - 4352

BT - Proceedings - IEEE International Symposium on Circuits and Systems

ER -

A macro-model for the efficient simulation of an ADC-based RNG

Abstract

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