A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities

Carmine Paolino; Fabio Pareschi; Mauro Mangia; Riccardo Rovatti; Gianluca Setti

doi:10.1109/PRIME.2019.8787816

A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities

Carmine Paolino, Fabio Pareschi, Mauro Mangia, Riccardo Rovatti, Gianluca Setti

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

In this paper we propose an innovative A/D architecture with the ability to acquire an input signal according to the recently introduced Compressed Sensing (CS) paradigm. The architecture relies on the hardware blocks already found in traditional successive-approximation-register (SAR) A/D converter, requiring only the addition of a limited number of switches. The capacitive array at the core of the circuit is used both by the SAR conversion algorithm and to realize the linear combination of consecutive signal samples, as required by the CS framework. The lack of additional active blocks allows for a remarkable saving in sampling energy with respect to published solutions. The role of some design parameters is investigated and solutions to ease the circuital implementation are analyzed.

Original language	English (US)
Title of host publication	PRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	133-136
Number of pages	4
ISBN (Print)	9781728135496
DOIs	https://doi.org/10.1109/PRIME.2019.8787816
State	Published - Jul 1 2019
Externally published	Yes

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10.1109/PRIME.2019.8787816

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Paolino, C., Pareschi, F., Mangia, M., Rovatti, R., & Setti, G. (2019). A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities. In PRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings (pp. 133-136). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME.2019.8787816

@inproceedings{a9554b2d092248a6a4c55f968161531c,

title = "A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities",

abstract = "In this paper we propose an innovative A/D architecture with the ability to acquire an input signal according to the recently introduced Compressed Sensing (CS) paradigm. The architecture relies on the hardware blocks already found in traditional successive-approximation-register (SAR) A/D converter, requiring only the addition of a limited number of switches. The capacitive array at the core of the circuit is used both by the SAR conversion algorithm and to realize the linear combination of consecutive signal samples, as required by the CS framework. The lack of additional active blocks allows for a remarkable saving in sampling energy with respect to published solutions. The role of some design parameters is investigated and solutions to ease the circuital implementation are analyzed.",

author = "Carmine Paolino and Fabio Pareschi and Mauro Mangia and Riccardo Rovatti and Gianluca Setti",

note = "Generated from Scopus record by KAUST IRTS on 2023-02-15",

year = "2019",

month = jul,

day = "1",

doi = "10.1109/PRIME.2019.8787816",

language = "English (US)",

isbn = "9781728135496",

pages = "133--136",

booktitle = "PRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

}

A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities. / Paolino, Carmine; Pareschi, Fabio; Mangia, Mauro et al.
PRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. p. 133-136.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities

AU - Paolino, Carmine

AU - Pareschi, Fabio

AU - Mangia, Mauro

AU - Rovatti, Riccardo

AU - Setti, Gianluca

N1 - Generated from Scopus record by KAUST IRTS on 2023-02-15

PY - 2019/7/1

Y1 - 2019/7/1

N2 - In this paper we propose an innovative A/D architecture with the ability to acquire an input signal according to the recently introduced Compressed Sensing (CS) paradigm. The architecture relies on the hardware blocks already found in traditional successive-approximation-register (SAR) A/D converter, requiring only the addition of a limited number of switches. The capacitive array at the core of the circuit is used both by the SAR conversion algorithm and to realize the linear combination of consecutive signal samples, as required by the CS framework. The lack of additional active blocks allows for a remarkable saving in sampling energy with respect to published solutions. The role of some design parameters is investigated and solutions to ease the circuital implementation are analyzed.

AB - In this paper we propose an innovative A/D architecture with the ability to acquire an input signal according to the recently introduced Compressed Sensing (CS) paradigm. The architecture relies on the hardware blocks already found in traditional successive-approximation-register (SAR) A/D converter, requiring only the addition of a limited number of switches. The capacitive array at the core of the circuit is used both by the SAR conversion algorithm and to realize the linear combination of consecutive signal samples, as required by the CS framework. The lack of additional active blocks allows for a remarkable saving in sampling energy with respect to published solutions. The role of some design parameters is investigated and solutions to ease the circuital implementation are analyzed.

UR - https://ieeexplore.ieee.org/document/8787816/

UR - http://www.scopus.com/inward/record.url?scp=85071342260&partnerID=8YFLogxK

U2 - 10.1109/PRIME.2019.8787816

DO - 10.1109/PRIME.2019.8787816

M3 - Conference contribution

SN - 9781728135496

SP - 133

EP - 136

BT - PRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities

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