This brief presents a pseudorandom number generator that requires very low resources from the hardware design point of view. It is based on a chain of digital accumulators whose coefficients are varied by an auxiliary low-complexity linear feedback shift register. We present a predictability and periodicity analysis of the sequences generated by the proposed architecture to show that the system is a good candidate to be used for applications requiring high-quality pseudorandom sequences in portable devices. The statistical behavior of the proposed solution is also validated by tests from the National Institute of Standards and Technology. The generated pseudorandom sequences pass all tests at both the level-one and level-two approaches. © 2011 IEEE.
|Original language||English (US)|
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|State||Published - Jan 1 2011|
ASJC Scopus subject areas
- Electrical and Electronic Engineering