TY - GEN
T1 - A Reconfigurable Synchrophasor Synchronization Gateway & Controller Architecture for DERs
AU - Adhikari, Prottay M.
AU - Vanfretti, Luigi
AU - Mishra, Chetan
AU - Jones, Kevin D.
N1 - KAUST Repository Item: Exported on 2022-09-14
Acknowledgements: This work was funded in part by the New York State Energy Research and Development Authority (NYSERDA) under grant agreement numbers 137948 and 149165, in part by Dominion Energy, and in part by the Center of Excellence for NEOM Research at King Abdullah University of Science and Technology
This publication acknowledges KAUST support, but has no KAUST affiliated authors.
PY - 2022/6/29
Y1 - 2022/6/29
N2 - In grid applications featuring various Distributed Energy Resources (DERs), e.g. microgrids, synchrophasor applications would require an extensive infrastructure including substantial instrumentation-hardware, communication network extensions and controller installations, like in WAMPAC systems. Thus, such overall implementation becomes cost-prohibitive. To address this issue, this paper proposes a dedicated centralized synchronization hardware to replace aggregation PDCs, and supplementary control functions into a single piece of hardware. This particular hardware is termed as Synchrophasor Synchronization Gateway & Controller (SSGC). The proposed SSGC hardware utilizes the Khorjin library to parse IEEE C37.118 data, concurrently from multiple devices, and in an embedded hard real-time (RT) computer system through a synchronization layer. Supplementary control actions, e.g. power flow control, are implemented on top of the synchronization layer. This SSGC based architecture is tested with a RT microgrid model implemented on Typhoon HIL-604 RT simulator. The communication interface between the micrgrid and the SSGC was tampered through external hardware by introducing network delays & data-drops, and its performance was analyzed.
AB - In grid applications featuring various Distributed Energy Resources (DERs), e.g. microgrids, synchrophasor applications would require an extensive infrastructure including substantial instrumentation-hardware, communication network extensions and controller installations, like in WAMPAC systems. Thus, such overall implementation becomes cost-prohibitive. To address this issue, this paper proposes a dedicated centralized synchronization hardware to replace aggregation PDCs, and supplementary control functions into a single piece of hardware. This particular hardware is termed as Synchrophasor Synchronization Gateway & Controller (SSGC). The proposed SSGC hardware utilizes the Khorjin library to parse IEEE C37.118 data, concurrently from multiple devices, and in an embedded hard real-time (RT) computer system through a synchronization layer. Supplementary control actions, e.g. power flow control, are implemented on top of the synchronization layer. This SSGC based architecture is tested with a RT microgrid model implemented on Typhoon HIL-604 RT simulator. The communication interface between the micrgrid and the SSGC was tampered through external hardware by introducing network delays & data-drops, and its performance was analyzed.
UR - http://hdl.handle.net/10754/680017
UR - https://ieeexplore.ieee.org/document/9806013/
UR - http://www.scopus.com/inward/record.url?scp=85134251408&partnerID=8YFLogxK
U2 - 10.1109/SGSMA51733.2022.9806013
DO - 10.1109/SGSMA51733.2022.9806013
M3 - Conference contribution
SN - 9789531842822
BT - 2022 International Conference on Smart Grid Synchronized Measurements and Analytics (SGSMA)
PB - IEEE
ER -