TY - GEN
T1 - A Self-Biased Schmitt Trigger for Low Power Applications
AU - Al-Qadasi, Mohammed
AU - Alshehri, Abdullah
AU - Al Attar, Talal
AU - Fariborzi, Hossein
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2019/1/24
Y1 - 2019/1/24
N2 - In this paper, a novel technique for enhancement of hysteresis comparators is proposed. This work is based on an improved version of hysteresis comparators that used NMOS current mirrors, a PMOS load stage and a PMOS tail transistor to reduce the static power. By using an internal biasing technique for the tail transistor, we eliminated the need for one of the biasing circuits while achieving 65% lower power consumption in 0.18μ m CMOS technology, without much impact on the trip values of the hysteresis comparator.
AB - In this paper, a novel technique for enhancement of hysteresis comparators is proposed. This work is based on an improved version of hysteresis comparators that used NMOS current mirrors, a PMOS load stage and a PMOS tail transistor to reduce the static power. By using an internal biasing technique for the tail transistor, we eliminated the need for one of the biasing circuits while achieving 65% lower power consumption in 0.18μ m CMOS technology, without much impact on the trip values of the hysteresis comparator.
UR - http://hdl.handle.net/10754/631287
UR - https://ieeexplore.ieee.org/document/8618032
UR - http://www.scopus.com/inward/record.url?scp=85062260829&partnerID=8YFLogxK
U2 - 10.1109/icecs.2018.8618032
DO - 10.1109/icecs.2018.8618032
M3 - Conference contribution
SN - 9781538695623
SP - 373
EP - 376
BT - 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -