A SIMO DC-DC boost converter with high efficiency and small area

Zaffar Hayat Nawaz Khan; Nabeel Ahmad; Danial Khan; Hamed Abbasizadeh; Syed Adii Ali Shah; Young Jun Park; Kang Yoon Lee

doi:10.23919/ELINFOCOM.2018.8330673

A SIMO DC-DC boost converter with high efficiency and small area

Zaffar Hayat Nawaz Khan, Nabeel Ahmad, Danial Khan, Hamed Abbasizadeh, Syed Adii Ali Shah, Young Jun Park, Kang Yoon Lee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

In this paper, a small area and a high efficiency Single Inductor Multiple Output (SIMO) Boost converter with Digital Pulse Width Modulation (DPWM) using Interlaced Hysteresis Delay Cells (IHDCs) is proposed. This technique has advantage of small area and high efficiency from prior works. The DPWM is composed of Delay Line using Interlaced Hysteresis Delay Cells. The fabrication CMOS Process is 55nm with a standard supply voltage of 1.8V and having 2.2V and 2.4V at its output. The area occupied by the chip is about 170μm × 190μm and efficiency is 94.00%.

Original language	English (US)
Title of host publication	International Conference on Electronics, Information and Communication, ICEIC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Print)	9781538647547
DOIs	https://doi.org/10.23919/ELINFOCOM.2018.8330673
State	Published - Apr 2 2018
Externally published	Yes

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10.23919/ELINFOCOM.2018.8330673

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Khan, Z. H. N., Ahmad, N., Khan, D., Abbasizadeh, H., Shah, S. A. A., Park, Y. J., & Lee, K. Y. (2018). A SIMO DC-DC boost converter with high efficiency and small area. In International Conference on Electronics, Information and Communication, ICEIC 2018 (pp. 1-3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/ELINFOCOM.2018.8330673

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title = "A SIMO DC-DC boost converter with high efficiency and small area",

abstract = "In this paper, a small area and a high efficiency Single Inductor Multiple Output (SIMO) Boost converter with Digital Pulse Width Modulation (DPWM) using Interlaced Hysteresis Delay Cells (IHDCs) is proposed. This technique has advantage of small area and high efficiency from prior works. The DPWM is composed of Delay Line using Interlaced Hysteresis Delay Cells. The fabrication CMOS Process is 55nm with a standard supply voltage of 1.8V and having 2.2V and 2.4V at its output. The area occupied by the chip is about 170μm × 190μm and efficiency is 94.00%.",

author = "Khan, {Zaffar Hayat Nawaz} and Nabeel Ahmad and Danial Khan and Hamed Abbasizadeh and Shah, {Syed Adii Ali} and Park, {Young Jun} and Lee, {Kang Yoon}",

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A SIMO DC-DC boost converter with high efficiency and small area. / Khan, Zaffar Hayat Nawaz; Ahmad, Nabeel; Khan, Danial et al.
International Conference on Electronics, Information and Communication, ICEIC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-3.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A SIMO DC-DC boost converter with high efficiency and small area

AU - Khan, Zaffar Hayat Nawaz

AU - Ahmad, Nabeel

AU - Khan, Danial

AU - Abbasizadeh, Hamed

AU - Shah, Syed Adii Ali

AU - Park, Young Jun

AU - Lee, Kang Yoon

N1 - Generated from Scopus record by KAUST IRTS on 2023-09-23

PY - 2018/4/2

Y1 - 2018/4/2

N2 - In this paper, a small area and a high efficiency Single Inductor Multiple Output (SIMO) Boost converter with Digital Pulse Width Modulation (DPWM) using Interlaced Hysteresis Delay Cells (IHDCs) is proposed. This technique has advantage of small area and high efficiency from prior works. The DPWM is composed of Delay Line using Interlaced Hysteresis Delay Cells. The fabrication CMOS Process is 55nm with a standard supply voltage of 1.8V and having 2.2V and 2.4V at its output. The area occupied by the chip is about 170μm × 190μm and efficiency is 94.00%.

AB - In this paper, a small area and a high efficiency Single Inductor Multiple Output (SIMO) Boost converter with Digital Pulse Width Modulation (DPWM) using Interlaced Hysteresis Delay Cells (IHDCs) is proposed. This technique has advantage of small area and high efficiency from prior works. The DPWM is composed of Delay Line using Interlaced Hysteresis Delay Cells. The fabrication CMOS Process is 55nm with a standard supply voltage of 1.8V and having 2.2V and 2.4V at its output. The area occupied by the chip is about 170μm × 190μm and efficiency is 94.00%.

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DO - 10.23919/ELINFOCOM.2018.8330673

M3 - Conference contribution

SN - 9781538647547

SP - 1

EP - 3

BT - International Conference on Electronics, Information and Communication, ICEIC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

A SIMO DC-DC boost converter with high efficiency and small area

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