TY - GEN
T1 - A system-level exploration of power delivery architectures for near-threshold manycores considering performance constraints
AU - Stamelakos, Ioannis
AU - Khajeh, Amin
AU - Eltawil, Ahmed
AU - Palermo, Gianluca
AU - Silvano, Cristina
AU - Kurdahi, Fadi
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2016/9/2
Y1 - 2016/9/2
N2 - Continuous technology scaling and increased demand for computational power have introduced a paradigm shift in manycore design requirements. On the other hand, tight power budgets and limitations of voltage scaling are throttling the ability to optimally exploit the potential of these systems, leading researchers to adopt aggressive voltage scaling techniques such as Near-Threshold Computing (NTC). In this paper we evaluate and compare the efficiency of different power delivery schemes for NT manycore architectures under process variation while meeting performance constraints. For platforms operating in a specific voltage range, simple and cost effective Power Delivery (PD) architectures can deliver average power savings ranging from 24% up to 50%, when taking into account the workload characteristics of the target applications at design time1.
AB - Continuous technology scaling and increased demand for computational power have introduced a paradigm shift in manycore design requirements. On the other hand, tight power budgets and limitations of voltage scaling are throttling the ability to optimally exploit the potential of these systems, leading researchers to adopt aggressive voltage scaling techniques such as Near-Threshold Computing (NTC). In this paper we evaluate and compare the efficiency of different power delivery schemes for NT manycore architectures under process variation while meeting performance constraints. For platforms operating in a specific voltage range, simple and cost effective Power Delivery (PD) architectures can deliver average power savings ranging from 24% up to 50%, when taking into account the workload characteristics of the target applications at design time1.
UR - http://ieeexplore.ieee.org/document/7560245/
UR - http://www.scopus.com/inward/record.url?scp=84988956551&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2016.65
DO - 10.1109/ISVLSI.2016.65
M3 - Conference contribution
SN - 9781467390385
BT - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
PB - IEEE Computer [email protected]
ER -