TY - GEN
T1 - A threat-based Connect6 implementation on FPGA
AU - Vipin, Kizheppatt
AU - Fahmy, Suhaib A.
N1 - Generated from Scopus record by KAUST IRTS on 2021-03-16
PY - 2011/12/1
Y1 - 2011/12/1
N2 - Connect6 is a new generation k-in-a-row game, which has drawn great interest not only from game enthusiasts, but also from researchers, due to its characteristics such as fairness and high state-space complexity. In this paper we describe the design and implementation of an FPGA-based Connect6 player that can compete against other computer-based opponents, communicating through a serial interface. Our algorithmic implementation utilises only basic FPGA building blocks such as LUTs and flip-flops and does not include any IP cores or hardware macros, making it portable across different FPGA platforms without design modifications. The design has been implemented and validated both on a Xilinx Spartan-3A, and a Xilinx Spartan-6 FPGA boards. The algorithm uses a powerful threat-based placement strategy that maximises the FPGA's winning opportunity while reducing the opponent's options. Extended simulation and evaluation based on software and human players confirms that our FPGA-based implementation performs well, and the algorithm used in the design leads to a high probability of success. © 2011 IEEE.
AB - Connect6 is a new generation k-in-a-row game, which has drawn great interest not only from game enthusiasts, but also from researchers, due to its characteristics such as fairness and high state-space complexity. In this paper we describe the design and implementation of an FPGA-based Connect6 player that can compete against other computer-based opponents, communicating through a serial interface. Our algorithmic implementation utilises only basic FPGA building blocks such as LUTs and flip-flops and does not include any IP cores or hardware macros, making it portable across different FPGA platforms without design modifications. The design has been implemented and validated both on a Xilinx Spartan-3A, and a Xilinx Spartan-6 FPGA boards. The algorithm uses a powerful threat-based placement strategy that maximises the FPGA's winning opportunity while reducing the opponent's options. Extended simulation and evaluation based on software and human players confirms that our FPGA-based implementation performs well, and the algorithm used in the design leads to a high probability of success. © 2011 IEEE.
UR - http://ieeexplore.ieee.org/document/6132745/
UR - http://www.scopus.com/inward/record.url?scp=84857229430&partnerID=8YFLogxK
U2 - 10.1109/FPT.2011.6132745
DO - 10.1109/FPT.2011.6132745
M3 - Conference contribution
SN - 9781457717406
BT - 2011 International Conference on Field-Programmable Technology, FPT 2011
ER -