Accurate analytical delay modeling of CMOS clock buffers considering power supply variations

Engineering

• Power Supply 100%
• Simulation Result 33%
• Capacitive 33%
• Circuit Simulation 33%
• Resistive 33%
• Parameter Variation 33%
• Circuit Parameter 33%
• Interconnects 33%
• Analytical Model 33%

Keyphrases

• Buffer Delay 50%
• Supply Parameters 50%
• Power Circuit 50%
• Drain Saturation Current 50%