Aggressively scaled high-k gate dielectric with excellent performance and high temperature stability for 32nm and beyond

P. Sivasubramani*, P. D. Kirsch, J. Huang, C. Park, Y. N. Tan, D. C. Gilmer, C. Young, K. Freeman, M. M. Hussain, R. Harris, S. C. Song, D. Heh, R. Choi, Cp Majhi, G. Bersuker, P. Lysaght, B. H. Lee, H. H. Tseng, I. J.S. Jur, D. J. LichtenwalnerA. I. Kingon, R. Jammy

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

14 Scopus citations

Abstract

We demonstrate an amorphous higher-k (k>20) HfTiSiON gate dielectric for sub 32nm node capable of low equivalent oxide thickness (EOT=0.84nm). For the first time, we have addressed the thermodynamic instability of TiO 2-containing gate dielectrics achieving an acceptably thin SiO x interface (0.7nm) after 1070°C. 3-lOx leakage current reduction is achieved with HfTiSiON vs. HfSiON due to a higher-k TiO2 cap (k=40) on HfSiON. For the first time, an 8% Ion-Ioff improvement of HfTiSiON vs. HfSiON is demonstrated. HfTiSiON shows I on=1300 μA/μm at Ioff=100nA/μm for V dd= 1.2V without stress engineering. HfTiSiON shows bias temperature instability (PBTI) and time dependent dielectric breakdown (TDDB) similar to HfSiON. This work is significant because it demonstrates higher-k scaling benefit and extension of high-k beyond Hf-oxides for sub-32nm technologies.

Original languageEnglish (US)
Article number4418995
Pages (from-to)543-546
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
StatePublished - 2007
Externally publishedYes
Event2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States
Duration: Dec 10 2007Dec 12 2007

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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