Abstract
We demonstrate an amorphous higher-k (k>20) HfTiSiON gate dielectric for sub 32nm node capable of low equivalent oxide thickness (EOT=0.84nm). For the first time, we have addressed the thermodynamic instability of TiO 2-containing gate dielectrics achieving an acceptably thin SiO x interface (0.7nm) after 1070°C. 3-lOx leakage current reduction is achieved with HfTiSiON vs. HfSiON due to a higher-k TiO2 cap (k=40) on HfSiON. For the first time, an 8% Ion-Ioff improvement of HfTiSiON vs. HfSiON is demonstrated. HfTiSiON shows I on=1300 μA/μm at Ioff=100nA/μm for V dd= 1.2V without stress engineering. HfTiSiON shows bias temperature instability (PBTI) and time dependent dielectric breakdown (TDDB) similar to HfSiON. This work is significant because it demonstrates higher-k scaling benefit and extension of high-k beyond Hf-oxides for sub-32nm technologies.
Original language | English (US) |
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Article number | 4418995 |
Pages (from-to) | 543-546 |
Number of pages | 4 |
Journal | Technical Digest - International Electron Devices Meeting, IEDM |
DOIs | |
State | Published - 2007 |
Externally published | Yes |
Event | 2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States Duration: Dec 10 2007 → Dec 12 2007 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry