TY - JOUR
T1 - Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits
AU - Hanna, Amir
AU - Hussain, Aftab M.
AU - Omran, Hesham
AU - Alshareef, Sarah
AU - Salama, Khaled N.
AU - Hussain, Muhammad Mustafa
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2015/12/4
Y1 - 2015/12/4
N2 - High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.
AB - High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.
UR - http://hdl.handle.net/10754/583279
UR - http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7347334
UR - http://www.scopus.com/inward/record.url?scp=84962014133&partnerID=8YFLogxK
U2 - 10.1109/LED.2015.2505613
DO - 10.1109/LED.2015.2505613
M3 - Article
SN - 0741-3106
VL - 37
SP - 193
EP - 196
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
IS - 2
ER -