An Efficient 2D Discrete Cosine Transform Processor for Multimedia Applications

Hasan Erdem Yantir, Ahmed Eltawil, Khaled N. Salama

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The memory bottleneck is the biggest concern affecting the scalability of traditional computer architectures. Furthermore, the necessity of applications to process the huge amount of data is increasing, especially after the evaluation of artificial intelligence (AI). This fact forces researchers to move through the more data-centric architectures rather than the existing processor centric ones. In-memory processors are such architecture that combines the memory and processor in the same location to eliminate the memory bottleneck. Associative processors are an ideal candidate for in-memory computation, especially for signal processing since the data is a key point in these applications. To demonstrate this, 2D DCT is implemented in associate in-memory processors. According to the comparison with the state of the art hardware realization, the proposed accelerator achieves the best energy efficiency for 4K HD inputs at 30 frames per second.
Original languageEnglish (US)
Title of host publication2020 28th Signal Processing and Communications Applications Conference (SIU)
ISBN (Print)9781728172064
StatePublished - Oct 5 2020


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