An efficient real-time FPGA implementation for object detection

Jin Zhao; Xinming Huang; Yehia Massoud

doi:10.1109/NEWCAS.2014.6934045

An efficient real-time FPGA implementation for object detection

Jin Zhao, Xinming Huang, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

In this paper, we present an efficient real-time FPGA implementation for object detection. The system employs Speeded Up Robust Features (SURF) algorithm to detect keypoints on every video frame and applies Fast Retina Keypoint (FREAK) method to describe the keypoints. One-to-one feature matching is performed between the descriptors of objects in the library and the descriptors of the video frames, to ensure a high object detection accuracy. Our experiments demonstrate that our FPGA-based design is fully functional and it can process video frames with 800×600 resolution at 60 fps. The proposed FPGA design is 23 times faster than the same algorithm implemented on Intel Core i5-3210M CPU.

Original language	English (US)
Title of host publication	2014 IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	313-316
Number of pages	4
ISBN (Print)	9781479948857
DOIs	https://doi.org/10.1109/NEWCAS.2014.6934045
State	Published - Oct 22 2014
Externally published	Yes

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10.1109/NEWCAS.2014.6934045

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@inproceedings{4c61ae1f4cf24e579577418c01298f8e,

title = "An efficient real-time FPGA implementation for object detection",

abstract = "In this paper, we present an efficient real-time FPGA implementation for object detection. The system employs Speeded Up Robust Features (SURF) algorithm to detect keypoints on every video frame and applies Fast Retina Keypoint (FREAK) method to describe the keypoints. One-to-one feature matching is performed between the descriptors of objects in the library and the descriptors of the video frames, to ensure a high object detection accuracy. Our experiments demonstrate that our FPGA-based design is fully functional and it can process video frames with 800×600 resolution at 60 fps. The proposed FPGA design is 23 times faster than the same algorithm implemented on Intel Core i5-3210M CPU.",

author = "Jin Zhao and Xinming Huang and Yehia Massoud",

note = "Generated from Scopus record by KAUST IRTS on 2022-09-13",

year = "2014",

month = oct,

day = "22",

doi = "10.1109/NEWCAS.2014.6934045",

language = "English (US)",

isbn = "9781479948857",

pages = "313--316",

booktitle = "2014 IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

}

TY - GEN

T1 - An efficient real-time FPGA implementation for object detection

AU - Zhao, Jin

AU - Huang, Xinming

AU - Massoud, Yehia

N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13

PY - 2014/10/22

Y1 - 2014/10/22

N2 - In this paper, we present an efficient real-time FPGA implementation for object detection. The system employs Speeded Up Robust Features (SURF) algorithm to detect keypoints on every video frame and applies Fast Retina Keypoint (FREAK) method to describe the keypoints. One-to-one feature matching is performed between the descriptors of objects in the library and the descriptors of the video frames, to ensure a high object detection accuracy. Our experiments demonstrate that our FPGA-based design is fully functional and it can process video frames with 800×600 resolution at 60 fps. The proposed FPGA design is 23 times faster than the same algorithm implemented on Intel Core i5-3210M CPU.

AB - In this paper, we present an efficient real-time FPGA implementation for object detection. The system employs Speeded Up Robust Features (SURF) algorithm to detect keypoints on every video frame and applies Fast Retina Keypoint (FREAK) method to describe the keypoints. One-to-one feature matching is performed between the descriptors of objects in the library and the descriptors of the video frames, to ensure a high object detection accuracy. Our experiments demonstrate that our FPGA-based design is fully functional and it can process video frames with 800×600 resolution at 60 fps. The proposed FPGA design is 23 times faster than the same algorithm implemented on Intel Core i5-3210M CPU.

UR - http://ieeexplore.ieee.org/document/6934045/

UR - http://www.scopus.com/inward/record.url?scp=84914692333&partnerID=8YFLogxK

U2 - 10.1109/NEWCAS.2014.6934045

DO - 10.1109/NEWCAS.2014.6934045

M3 - Conference contribution

SN - 9781479948857

SP - 313

EP - 316

BT - 2014 IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

An efficient real-time FPGA implementation for object detection

Abstract

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