TY - GEN
T1 - An Efficient Topology-Based Algorithm for Transient Analysis of Power Grid
AU - Yang, Lan
AU - Wang, Jingbin
AU - Azevedo, Lorenzo
AU - Wang, Jim Jing-Yan
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2015/8/11
Y1 - 2015/8/11
N2 - In the design flow of integrated circuits, chip-level verification is an important step that sanity checks the performance is as expected. Power grid verification is one of the most expensive and time-consuming steps of chip-level verification, due to its extremely large size. Efficient power grid analysis technology is highly demanded as it saves computing resources and enables faster iteration. In this paper, a topology-base power grid transient analysis algorithm is proposed. Nodal analysis is adopted to analyze the topology which is mathematically equivalent to iteratively solving a positive semi-definite linear equation. The convergence of the method is proved.
AB - In the design flow of integrated circuits, chip-level verification is an important step that sanity checks the performance is as expected. Power grid verification is one of the most expensive and time-consuming steps of chip-level verification, due to its extremely large size. Efficient power grid analysis technology is highly demanded as it saves computing resources and enables faster iteration. In this paper, a topology-base power grid transient analysis algorithm is proposed. Nodal analysis is adopted to analyze the topology which is mathematically equivalent to iteratively solving a positive semi-definite linear equation. The convergence of the method is proved.
UR - http://hdl.handle.net/10754/622132
UR - http://link.springer.com/10.1007/978-3-319-22180-9_65
UR - http://www.scopus.com/inward/record.url?scp=84943639098&partnerID=8YFLogxK
U2 - 10.1007/978-3-319-22180-9_65
DO - 10.1007/978-3-319-22180-9_65
M3 - Conference contribution
SN - 9783319221793
SP - 649
EP - 660
BT - Intelligent Computing Theories and Methodologies
PB - Springer Nature
ER -