An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

R. Khamankar; H. Bu; C. Bowen; S. Chakravarthi; P. R. Chidambaram; M. Bevan; A. Krishnan; H. Niimi; B. Smith; J. Blatchford; B. Hornung; J. P. Lu; P. Nicollian; B. Kirkpatrick; D. Miles; M. Hewson; D. Farber; L. Hall; H. AlShareef; A. Varghese; A. Gurba; V. Ukraintsev; B. Rathsack; J. DeLoach; J. Tran; C. Kaneshige; M. Somervell; S. Aur; C. Machala; T. Grider

doi:10.1109/vlsit.2004.1345456

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

R. Khamankar^*, H. Bu, C. Bowen, S. Chakravarthi, P. R. Chidambaram, M. Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J. P. Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall, H. AlShareef, A. VargheseA. Gurba, V. Ukraintsev, B. Rathsack, J. DeLoach, J. Tran, C. Kaneshige, M. Somervell, S. Aur, C. Machala, T. Grider

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

26 Scopus citations

Abstract

In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA/μm. An industry leading 90nm technology CV/I of 0.61ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12Å EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.

Original language	English (US)
Pages (from-to)	162-163
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/vlsit.2004.1345456
State	Published - 2004
Externally published	Yes
Event	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States Duration: Jun 15 2004 → Jun 17 2004

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/vlsit.2004.1345456

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Khamankar, R., Bu, H., Bowen, C., Chakravarthi, S., Chidambaram, P. R., Bevan, M., Krishnan, A., Niimi, H., Smith, B., Blatchford, J., Hornung, B., Lu, J. P., Nicollian, P., Kirkpatrick, B., Miles, D., Hewson, M., Farber, D., Hall, L., AlShareef, H., ... Grider, T. (2004). An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes. Digest of Technical Papers - Symposium on VLSI Technology, 162-163. https://doi.org/10.1109/vlsit.2004.1345456

@article{cb2c9d6580ab47e58e86e50d0e1b2d4c,

title = "An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes",

abstract = "In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA/μm. An industry leading 90nm technology CV/I of 0.61ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12{\AA} EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.",

author = "R. Khamankar and H. Bu and C. Bowen and S. Chakravarthi and Chidambaram, {P. R.} and M. Bevan and A. Krishnan and H. Niimi and B. Smith and J. Blatchford and B. Hornung and Lu, {J. P.} and P. Nicollian and B. Kirkpatrick and D. Miles and M. Hewson and D. Farber and L. Hall and H. AlShareef and A. Varghese and A. Gurba and V. Ukraintsev and B. Rathsack and J. DeLoach and J. Tran and C. Kaneshige and M. Somervell and S. Aur and C. Machala and T. Grider",

year = "2004",

doi = "10.1109/vlsit.2004.1345456",

language = "English (US)",

pages = "162--163",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",

}

Khamankar, R, Bu, H, Bowen, C, Chakravarthi, S, Chidambaram, PR, Bevan, M, Krishnan, A, Niimi, H, Smith, B, Blatchford, J, Hornung, B, Lu, JP, Nicollian, P, Kirkpatrick, B, Miles, D, Hewson, M, Farber, D, Hall, L, AlShareef, H, Varghese, A, Gurba, A, Ukraintsev, V, Rathsack, B, DeLoach, J, Tran, J, Kaneshige, C, Somervell, M, Aur, S, Machala, C & Grider, T 2004, 'An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes', Digest of Technical Papers - Symposium on VLSI Technology, pp. 162-163. https://doi.org/10.1109/vlsit.2004.1345456

TY - JOUR

T1 - An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

AU - Khamankar, R.

AU - Bu, H.

AU - Bowen, C.

AU - Chakravarthi, S.

AU - Chidambaram, P. R.

AU - Bevan, M.

AU - Krishnan, A.

AU - Niimi, H.

AU - Smith, B.

AU - Blatchford, J.

AU - Hornung, B.

AU - Lu, J. P.

AU - Nicollian, P.

AU - Kirkpatrick, B.

AU - Miles, D.

AU - Hewson, M.

AU - Farber, D.

AU - Hall, L.

AU - AlShareef, H.

AU - Varghese, A.

AU - Gurba, A.

AU - Ukraintsev, V.

AU - Rathsack, B.

AU - DeLoach, J.

AU - Tran, J.

AU - Kaneshige, C.

AU - Somervell, M.

AU - Aur, S.

AU - Machala, C.

AU - Grider, T.

PY - 2004

Y1 - 2004

N2 - In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA/μm. An industry leading 90nm technology CV/I of 0.61ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12Å EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.

AB - In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA/μm. An industry leading 90nm technology CV/I of 0.61ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12Å EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.

UR - http://www.scopus.com/inward/record.url?scp=4544318336&partnerID=8YFLogxK

U2 - 10.1109/vlsit.2004.1345456

DO - 10.1109/vlsit.2004.1345456

M3 - Conference article

AN - SCOPUS:4544318336

SN - 0743-1562

SP - 162

EP - 163

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

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