Predicting the performance of the ΣΔ analog to digital converters (ADCs) is a computationally expensive task that can take several days for estimating the performance. In this paper, we propose a new circuit/behavioral simulation framework for accurately estimating the performance of CT-ΣΔ-ADCs. Our framework is based on newly developed simulation-directed macro-models and associated mapping techniques for accurately modeling and simulating the CT-ΣΔ-ADCs in the presence of the various non-idealities. We validate our circuit/behavioral framework by the simulation of a 2 nd order low pass and a 4 th order band pass ADCs. Our newly developed framework predicts the performance degradation within an error less than 4% while achieving three orders of magnitude simulation speedup. Copyright 2006 ACM.
|Original language||English (US)|
|Title of host publication||Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|
|Number of pages||4|
|State||Published - Nov 16 2006|