Back-end-of-line integration of 2D materials on silicon microchips

M. Lanza*, S. Pazos, K. Zhu, Y. Yuan, Y. Shen, O. Alharbi, W. Zheng, X. Zhang, H. N. Alshareef

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Two-dimensional (2D) materials have excellent electronic and thermal properties that could help to improve the performance of electronic devices and circuits. However, scalable 2D materials synthesis and their integration in silicon microchips (with, for example, complementary metal-oxide-semiconductor, CMOS) transistors presents some challenges, mainly related to the presence of local defects that degrade device/circuit performance. In this invited article, we discuss the integration of 2D materials in silicon microchips. We analyze the type of materials and their properties, the main synthesis and manipulation methods, the type of circuits fabricated, the electronic performance achieved, as well as the future challenges and solutions. We focus on microchips with pre-patterned CMOS circuits on which the 2D material is deposited at the back-end-of-line (BEOL).

Original languageEnglish (US)
Title of host publication2023 International Electron Devices Meeting, IEDM 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350327670
DOIs
StatePublished - 2023
Event2023 International Electron Devices Meeting, IEDM 2023 - San Francisco, United States
Duration: Dec 9 2023Dec 13 2023

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2023 International Electron Devices Meeting, IEDM 2023
Country/TerritoryUnited States
CitySan Francisco
Period12/9/2312/13/23

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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