Band-engineered low PMOS vT with high-K/metal gates featured in a dual channel CMOS integration scheme

H. Rusty Harris; Pankaj Kalra; Prashant Majhi; Muhammed Hussain; David Kelly; Jungwoo Oh; Dawei He; Casey Smith; Joel Barnett; Paul D. Kirsch; Gabriel Gebara; Jess Jur; Daniel Lichtenwalner; Abigail Lubow; T. P. Ma; Guangyu Sung; Scott Thompson; Byoung Hun Lee; Hsing Huang Tseng; Raj Jammy

doi:10.1109/VLSIT.2007.4339763

Band-engineered low PMOS v_T with high-K/metal gates featured in a dual channel CMOS integration scheme

H. Rusty Harris, Pankaj Kalra, Prashant Majhi, Muhammed Hussain, David Kelly, Jungwoo Oh, Dawei He, Casey Smith, Joel Barnett, Paul D. Kirsch, Gabriel Gebara, Jess Jur, Daniel Lichtenwalner, Abigail Lubow, T. P. Ma, Guangyu Sung, Scott Thompson, Byoung Hun Lee, Hsing Huang Tseng, Raj Jammy

Research output: Contribution to journal › Conference article › peer-review

51 Scopus citations

Abstract

Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La ₂O₃ capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.

Original language	English (US)
Article number	4339763
Pages (from-to)	154-155
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2007.4339763
State	Published - 2007
Externally published	Yes
Event	2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan Duration: Jun 12 2007 → Jun 14 2007

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/VLSIT.2007.4339763

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Harris, H. R., Kalra, P., Majhi, P., Hussain, M., Kelly, D., Oh, J., He, D., Smith, C., Barnett, J., Kirsch, P. D., Gebara, G., Jur, J., Lichtenwalner, D., Lubow, A., Ma, T. P., Sung, G., Thompson, S., Lee, B. H., Tseng, H. H., & Jammy, R. (2007). Band-engineered low PMOS v_T with high-K/metal gates featured in a dual channel CMOS integration scheme. Digest of Technical Papers - Symposium on VLSI Technology, 154-155. Article 4339763. https://doi.org/10.1109/VLSIT.2007.4339763

@article{31dc9c6dfded438383095eb916ce1558,

title = "Band-engineered low PMOS vT with high-K/metal gates featured in a dual channel CMOS integration scheme",

abstract = "Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.",

author = "Harris, {H. Rusty} and Pankaj Kalra and Prashant Majhi and Muhammed Hussain and David Kelly and Jungwoo Oh and Dawei He and Casey Smith and Joel Barnett and Kirsch, {Paul D.} and Gabriel Gebara and Jess Jur and Daniel Lichtenwalner and Abigail Lubow and Ma, {T. P.} and Guangyu Sung and Scott Thompson and Lee, {Byoung Hun} and Tseng, {Hsing Huang} and Raj Jammy",

year = "2007",

doi = "10.1109/VLSIT.2007.4339763",

language = "English (US)",

pages = "154--155",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 Symposium on VLSI Technology, VLSIT 2007 ; Conference date: 12-06-2007 Through 14-06-2007",

}

Harris, HR, Kalra, P, Majhi, P, Hussain, M, Kelly, D, Oh, J, He, D, Smith, C, Barnett, J, Kirsch, PD, Gebara, G, Jur, J, Lichtenwalner, D, Lubow, A, Ma, TP, Sung, G, Thompson, S, Lee, BH, Tseng, HH & Jammy, R 2007, 'Band-engineered low PMOS v_T with high-K/metal gates featured in a dual channel CMOS integration scheme', Digest of Technical Papers - Symposium on VLSI Technology, pp. 154-155. https://doi.org/10.1109/VLSIT.2007.4339763

TY - JOUR

T1 - Band-engineered low PMOS vT with high-K/metal gates featured in a dual channel CMOS integration scheme

AU - Harris, H. Rusty

AU - Kalra, Pankaj

AU - Majhi, Prashant

AU - Hussain, Muhammed

AU - Kelly, David

AU - Oh, Jungwoo

AU - He, Dawei

AU - Smith, Casey

AU - Barnett, Joel

AU - Kirsch, Paul D.

AU - Gebara, Gabriel

AU - Jur, Jess

AU - Lichtenwalner, Daniel

AU - Lubow, Abigail

AU - Ma, T. P.

AU - Sung, Guangyu

AU - Thompson, Scott

AU - Lee, Byoung Hun

AU - Tseng, Hsing Huang

AU - Jammy, Raj

PY - 2007

Y1 - 2007

N2 - Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.

AB - Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.

UR - http://www.scopus.com/inward/record.url?scp=37549063505&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2007.4339763

DO - 10.1109/VLSIT.2007.4339763

M3 - Conference article

AN - SCOPUS:37549063505

SN - 0743-1562

SP - 154

EP - 155

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

M1 - 4339763

T2 - 2007 Symposium on VLSI Technology, VLSIT 2007

Y2 - 12 June 2007 through 14 June 2007

ER -

Band-engineered low PMOS v_T with high-K/metal gates featured in a dual channel CMOS integration scheme

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