TY - GEN
T1 - CMOS-RC Colpitts Oscillator Design Using Floating Fractional-Order Inductance Simulator
AU - Kartci, Aslihan
AU - Herencsar, Norbert
AU - Brancik, Lu bomir
AU - Salama, Khaled N.
N1 - KAUST Repository Item: Exported on 2020-10-01
Acknowledgements: The article is based on work from the COST Action CA15225, a network supported by COST (European Cooperation in Science and Technology). Research described in this paper was financed by the National Sustainability Program under grant no. LO1401 and by the Czech Science Foundation under grant no. 16-06175S. For the research, infrastructure of the SIX Center was used.
PY - 2019/2/28
Y1 - 2019/2/28
N2 - This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75 th order Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CF±s), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic resistance of CF± is used as design parameter instead of passive resistor. The resulting equivalent inductance value of the FoL can be adjusted via order of FoC, which was emulated via 5 th -order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 kHz - 2.45 MHz the L y shows ±5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±1 V supply voltages.
AB - This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75 th order Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CF±s), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic resistance of CF± is used as design parameter instead of passive resistor. The resulting equivalent inductance value of the FoL can be adjusted via order of FoC, which was emulated via 5 th -order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 kHz - 2.45 MHz the L y shows ±5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±1 V supply voltages.
UR - http://hdl.handle.net/10754/652976
UR - https://ieeexplore.ieee.org/document/8623859
UR - http://www.scopus.com/inward/record.url?scp=85062230475&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2018.8623859
DO - 10.1109/MWSCAS.2018.8623859
M3 - Conference contribution
SN - 9781538673928
SP - 905
EP - 908
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -