Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory

Md Hasan Raza Ansari, Nazek El-Atab*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work presents vertically stacked Nanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate all around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 μs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same Eox.

Original languageEnglish (US)
Title of host publication2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665459792
DOIs
StatePublished - 2022
Event2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022 - Honolulu, United States
Duration: Jun 11 2022Jun 12 2022

Publication series

Name2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022

Conference

Conference2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
Country/TerritoryUnited States
CityHonolulu
Period06/11/2206/12/22

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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