TY - GEN
T1 - Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory
AU - Ansari, Md Hasan Raza
AU - El-Atab, Nazek
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This work presents vertically stacked Nanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate all around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 μs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same Eox.
AB - This work presents vertically stacked Nanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate all around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 μs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same Eox.
UR - http://www.scopus.com/inward/record.url?scp=85141098533&partnerID=8YFLogxK
U2 - 10.1109/SNW56633.2022.9889062
DO - 10.1109/SNW56633.2022.9889062
M3 - Conference contribution
AN - SCOPUS:85141098533
T3 - 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
BT - 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
Y2 - 11 June 2022 through 12 June 2022
ER -