Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors

Y. Lin, P. C. Shen, C. Su, A. S. Chou, T. Wu, C. C. Cheng, J. H. Park, M. H. Chiu, A. Y. Lu, H. L. Tang, M. M. Tavakoli, G. Pitner, X. Ji, C. McGahan, X. Wang, Z. Cai, N. Mao, J. Wang, Y. Wang, W. TisdaleX. Ling, K. E. Aidala, Vincent Tung, J. Li, A. Zettl, C. I. Wu, Jing Guo, H. Wang, J. Bokor, T. Palacios, L. J. Li, J. Kong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Two-dimensional (2D) semiconductors are expected to have exceptional properties for ultimately scaled transistors, but forming ohmic contact to them has been challenging, which tremendously limit the transistor performance. In this paper, we review the recent research progress on the elimination of different gap-state pinning effects, including defect-induced gap states (DIGS) and metal-induced gap states (MIGS). Specifically, an oxygen passivation method and a semimetallic contact technology were developed to reduce the DIGS and MIGS, respectively. Based on these approaches, much improved contact resistance and on-state current were observed. Key device metrics were extracted on these high-performance transistors, which reveals future directions for further improving the device performance.
Original languageEnglish (US)
Title of host publication2021 IEEE International Electron Devices Meeting (IEDM)
PublisherIEEE
Pages37.2.1-37.2.4
ISBN (Print)9781665425728
DOIs
StatePublished - Dec 11 2021

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