Critical components of FinFET integration: Examining the density trade-off and process integration for FinFIT implementation

While the scaling efforts continue into a device regime performance simply may not come without large scale off state leakage issues, significant device changes are being considered such as FinFETs. The concept of a double- or triple-channel device is not new, but the practical roadblock to implementing such a device has some familiar problems from an integration standpoint. Furthermore, new issues that the 3-dimensionality of FinFETs presents create integration challenges for series resistance and overall packing density. In this paper, we outline the critical issues and present practical solutions to these problems from a theoretical standpoint. It is shown that clear pathways do exist in spacer, silicide and epitaxial source/drain with unit process development. Finally, the implementation of necessary techniques such as spacer transfer and compatibility with high k/metal gate integration is examined.