TY - GEN
T1 - Cross layer error exploitation for aggressive voltage scaling
AU - Djahromi, Amin Khajeh
AU - Eltawil, Ahmed M.
AU - Kurdahi, Fadi J.
AU - Kanj, Rouwaida
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2007/8/28
Y1 - 2007/8/28
N2 - This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3GPP WCDMA modem. © 2007 IEEE.
AB - This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3GPP WCDMA modem. © 2007 IEEE.
UR - http://ieeexplore.ieee.org/document/4149033/
UR - http://www.scopus.com/inward/record.url?scp=34548133522&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2007.53
DO - 10.1109/ISQED.2007.53
M3 - Conference contribution
SN - 0769527957
BT - Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
ER -