Demonstration of high performance transistors with PVD metal gate

H. R. Harris; H. C. Wen; K. Choi; H. Alshareef; H. Luan; Y. Senzaki; C. D. Young; S. C. Song; Z. Zhang; G. Bersuker; P. Majhi; B. H. Lee

doi:10.1109/ESSDER.2005.1546677

Demonstration of high performance transistors with PVD metal gate

H. R. Harris^*, H. C. Wen, K. Choi, H. Alshareef, H. Luan, Y. Senzaki, C. D. Young, S. C. Song, Z. Zhang, G. Bersuker, P. Majhi, B. H. Lee

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Transistors devices have been fabricated in the traditional gate-first approach with HfO₂ and PVD TaN as the gate electrode. The stability of the PVD metal with the high dielectric constant material is studied in terms of the gate leakage, capacitance, transistor properties and reliability. Comparison of the PVD devices with the same devices using ALD TaN is performed to understand the influence of the PVD process on device properties. It is concluded that PVD deposition of metal gates with 1000oC poly activation anneal can be performed with no measurable damage to the dielectric and full thermal stability. Furthermore, one can realize high performance transistors with proper engineering of the PVD process

Original language	English (US)
Title of host publication	Proceedings of ESSDERC 2005
Subtitle of host publication	35th European Solid-State Device Research Conference
Pages	431-434
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDER.2005.1546677
State	Published - 2005
Externally published	Yes
Event	ESSDERC 2005: 35th European Solid-State Device Research Conference - Grenoble, France Duration: Sep 12 2005 → Sep 16 2005

Publication series

Name	Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference
Volume	2005

Other

Other	ESSDERC 2005: 35th European Solid-State Device Research Conference
Country/Territory	France
City	Grenoble
Period	09/12/05 → 09/16/05

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/ESSDER.2005.1546677

Cite this

Harris, H. R., Wen, H. C., Choi, K., Alshareef, H., Luan, H., Senzaki, Y., Young, C. D., Song, S. C., Zhang, Z., Bersuker, G., Majhi, P., & Lee, B. H. (2005). Demonstration of high performance transistors with PVD metal gate. In Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference (pp. 431-434). Article 1546677 (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference; Vol. 2005). https://doi.org/10.1109/ESSDER.2005.1546677

@inproceedings{e6dd6de39ad849c4a4a1845073728702,

title = "Demonstration of high performance transistors with PVD metal gate",

abstract = "Transistors devices have been fabricated in the traditional gate-first approach with HfO2 and PVD TaN as the gate electrode. The stability of the PVD metal with the high dielectric constant material is studied in terms of the gate leakage, capacitance, transistor properties and reliability. Comparison of the PVD devices with the same devices using ALD TaN is performed to understand the influence of the PVD process on device properties. It is concluded that PVD deposition of metal gates with 1000oC poly activation anneal can be performed with no measurable damage to the dielectric and full thermal stability. Furthermore, one can realize high performance transistors with proper engineering of the PVD process",

author = "Harris, {H. R.} and Wen, {H. C.} and K. Choi and H. Alshareef and H. Luan and Y. Senzaki and Young, {C. D.} and Song, {S. C.} and Z. Zhang and G. Bersuker and P. Majhi and Lee, {B. H.}",

year = "2005",

doi = "10.1109/ESSDER.2005.1546677",

language = "English (US)",

isbn = "0780392035",

series = "Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference",

pages = "431--434",

booktitle = "Proceedings of ESSDERC 2005",

note = "ESSDERC 2005: 35th European Solid-State Device Research Conference ; Conference date: 12-09-2005 Through 16-09-2005",

}

Harris, HR, Wen, HC, Choi, K, Alshareef, H, Luan, H, Senzaki, Y, Young, CD, Song, SC, Zhang, Z, Bersuker, G, Majhi, P & Lee, BH 2005, Demonstration of high performance transistors with PVD metal gate. in Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference., 1546677, Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference, vol. 2005, pp. 431-434, ESSDERC 2005: 35th European Solid-State Device Research Conference, Grenoble, France, 09/12/05. https://doi.org/10.1109/ESSDER.2005.1546677

Demonstration of high performance transistors with PVD metal gate. / Harris, H. R.; Wen, H. C.; Choi, K. et al.
Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference. 2005. p. 431-434 1546677 (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Demonstration of high performance transistors with PVD metal gate

AU - Harris, H. R.

AU - Wen, H. C.

AU - Choi, K.

AU - Alshareef, H.

AU - Luan, H.

AU - Senzaki, Y.

AU - Young, C. D.

AU - Song, S. C.

AU - Zhang, Z.

AU - Bersuker, G.

AU - Majhi, P.

AU - Lee, B. H.

PY - 2005

Y1 - 2005

N2 - Transistors devices have been fabricated in the traditional gate-first approach with HfO2 and PVD TaN as the gate electrode. The stability of the PVD metal with the high dielectric constant material is studied in terms of the gate leakage, capacitance, transistor properties and reliability. Comparison of the PVD devices with the same devices using ALD TaN is performed to understand the influence of the PVD process on device properties. It is concluded that PVD deposition of metal gates with 1000oC poly activation anneal can be performed with no measurable damage to the dielectric and full thermal stability. Furthermore, one can realize high performance transistors with proper engineering of the PVD process

AB - Transistors devices have been fabricated in the traditional gate-first approach with HfO2 and PVD TaN as the gate electrode. The stability of the PVD metal with the high dielectric constant material is studied in terms of the gate leakage, capacitance, transistor properties and reliability. Comparison of the PVD devices with the same devices using ALD TaN is performed to understand the influence of the PVD process on device properties. It is concluded that PVD deposition of metal gates with 1000oC poly activation anneal can be performed with no measurable damage to the dielectric and full thermal stability. Furthermore, one can realize high performance transistors with proper engineering of the PVD process

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T3 - Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

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BT - Proceedings of ESSDERC 2005

T2 - ESSDERC 2005: 35th European Solid-State Device Research Conference

Y2 - 12 September 2005 through 16 September 2005

ER -

Demonstration of high performance transistors with PVD metal gate

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