Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

Matthew Spencer; Fred Chen; Cheng C. Wang; Rhesa Nathanael; Hossein Fariborzi; Abhinav Gupta; Hei Kam; Vincent Pott; Jaeseok Jeon; Tsu Jae King Liu; Dejan Marković; Elad Alon; Vladimir Stojanović

doi:10.1109/JSSC.2010.2074370

Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

Matthew Spencer^*, Fred Chen, Cheng C. Wang, Rhesa Nathanael, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu Jae King Liu, Dejan Marković, Elad Alon, Vladimir Stojanović

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

159 Scopus citations

Abstract

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.

Original language	English (US)
Article number	5617293
Pages (from-to)	308-320
Number of pages	13
Journal	IEEE Journal of Solid-State Circuits
Volume	46
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2010.2074370
State	Published - Jan 2011
Externally published	Yes

Keywords

Adders
MEM relays
digital circuits
microelectromechanical devices
minimum energy point
very-large-scale integration

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2010.2074370

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Spencer, M., Chen, F., Wang, C. C., Nathanael, R., Fariborzi, H., Gupta, A., Kam, H., Pott, V., Jeon, J., Liu, T. J. K., Marković, D., Alon, E., & Stojanović, V. (2011). Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications. IEEE Journal of Solid-State Circuits, 46(1), 308-320. Article 5617293. https://doi.org/10.1109/JSSC.2010.2074370

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abstract = "This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.",

keywords = "Adders, MEM relays, digital circuits, microelectromechanical devices, minimum energy point, very-large-scale integration",

author = "Matthew Spencer and Fred Chen and Wang, {Cheng C.} and Rhesa Nathanael and Hossein Fariborzi and Abhinav Gupta and Hei Kam and Vincent Pott and Jaeseok Jeon and Liu, {Tsu Jae King} and Dejan Markovi{\'c} and Elad Alon and Vladimir Stojanovi{\'c}",

note = "Funding Information: Manuscript received April 20, 2010; revised July 05, 2010; accepted July 16, 2010. Date of publication November 01, 2010; date of current version December 27, 2010. This paper was approved by Guest Editor Alison Burdett. This work was supported in part by the DARPA NEMS program, the C2S2 and MSD FCRP centers, MIT CICS, UCLA ICSL, BWRC, and NSF Infrastructure Grant No. 040327.",

year = "2011",

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doi = "10.1109/JSSC.2010.2074370",

language = "English (US)",

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AU - Alon, Elad

AU - Stojanović, Vladimir

N1 - Funding Information: Manuscript received April 20, 2010; revised July 05, 2010; accepted July 16, 2010. Date of publication November 01, 2010; date of current version December 27, 2010. This paper was approved by Guest Editor Alison Burdett. This work was supported in part by the DARPA NEMS program, the C2S2 and MSD FCRP centers, MIT CICS, UCLA ICSL, BWRC, and NSF Infrastructure Grant No. 040327.

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AB - This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.

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Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

Abstract

Keywords

ASJC Scopus subject areas

UN SDGs

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