TY - JOUR
T1 - Design and implementation of a scalable channel emulator for wideband MIMO systems
AU - Eslami, Hamid
AU - Tran, Sang V.
AU - Eltawil, Ahmed M.
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2009/11/1
Y1 - 2009/11/1
N2 - Wireless channel emulation is becoming increasingly important, particularly with the advent of multiple-inputmultiple-output (MIMO) systems, where system performance is highly dependent on the accurate representation of the channel condition. In this paper, we compare the conventional finite impulse response (FIR)-based emulator versus solely performing the emulation in the frequency domain. We show that for single-inputsingle-output (SISO) systems, FIR-based emulators are computationally efficient but that the complexity rapidly becomes impractical for larger array sizes. On the other hand, frequency-domain approaches exhibit a fixed initial complexity cost that grows at a reduced rate as a function of the array size, resulting in significant savings in complexity for higher order arrays. As an illustrative example of this approach, field-programmable gate array (FPGA) architecture implementing a sample 3 × 3 MIMO system exhibits resource savings of up to 67% over a similarly constrained FIR approach. The architecture is discussed in detail, and implementation results, as well as laboratory measurements, are presented. © 2009 IEEE.
AB - Wireless channel emulation is becoming increasingly important, particularly with the advent of multiple-inputmultiple-output (MIMO) systems, where system performance is highly dependent on the accurate representation of the channel condition. In this paper, we compare the conventional finite impulse response (FIR)-based emulator versus solely performing the emulation in the frequency domain. We show that for single-inputsingle-output (SISO) systems, FIR-based emulators are computationally efficient but that the complexity rapidly becomes impractical for larger array sizes. On the other hand, frequency-domain approaches exhibit a fixed initial complexity cost that grows at a reduced rate as a function of the array size, resulting in significant savings in complexity for higher order arrays. As an illustrative example of this approach, field-programmable gate array (FPGA) architecture implementing a sample 3 × 3 MIMO system exhibits resource savings of up to 67% over a similarly constrained FIR approach. The architecture is discussed in detail, and implementation results, as well as laboratory measurements, are presented. © 2009 IEEE.
UR - http://ieeexplore.ieee.org/document/5164969/
UR - http://www.scopus.com/inward/record.url?scp=70450160472&partnerID=8YFLogxK
U2 - 10.1109/TVT.2009.2027439
DO - 10.1109/TVT.2009.2027439
M3 - Article
SN - 0018-9545
VL - 58
JO - IEEE Transactions on Vehicular Technology
JF - IEEE Transactions on Vehicular Technology
IS - 9
ER -