TY - JOUR
T1 - Design and realization of variable digital filters for software-defined radio channelizers using an improved coefficient decimation method
AU - Ambede, Abhishek
AU - Shreejith, Shanker
AU - Vinod, A. P.
AU - Fahmy, Suhaib A.
N1 - Generated from Scopus record by KAUST IRTS on 2021-03-16
PY - 2016/1/1
Y1 - 2016/1/1
N2 - Variable digital filters (VDFs) are used in software-defined radio handsets for extraction of individual radio channels corresponding to multiple wireless communication standards. In this brief, we propose a VDF based on the improved coefficient decimation method. The proposed VDF provides variable low-pass, high-pass, bandpass, bandstop, and multiband frequency responses on the fly, using the same set of prototype filter coefficients. We present nonpipelined and pipelined implementation architectures for the proposed VDF, along with field-programmable gate array implementation results for multiple VDF designs. Analysis of the implementation results shows that the pipelined implementations achieve average reductions of 27.66%, 49.17%, and 25.59% in the number of occupied slices, dynamic power, and energy consumption, respectively, when compared with corresponding nonpipelined implementations. In addition, the proposed pipelined implementation architecture provides high operating frequencies that are independent of the prototype filter order across different VDF designs. An average maximum frequency of 157.89 MHz is obtained.
AB - Variable digital filters (VDFs) are used in software-defined radio handsets for extraction of individual radio channels corresponding to multiple wireless communication standards. In this brief, we propose a VDF based on the improved coefficient decimation method. The proposed VDF provides variable low-pass, high-pass, bandpass, bandstop, and multiband frequency responses on the fly, using the same set of prototype filter coefficients. We present nonpipelined and pipelined implementation architectures for the proposed VDF, along with field-programmable gate array implementation results for multiple VDF designs. Analysis of the implementation results shows that the pipelined implementations achieve average reductions of 27.66%, 49.17%, and 25.59% in the number of occupied slices, dynamic power, and energy consumption, respectively, when compared with corresponding nonpipelined implementations. In addition, the proposed pipelined implementation architecture provides high operating frequencies that are independent of the prototype filter order across different VDF designs. An average maximum frequency of 157.89 MHz is obtained.
UR - https://ieeexplore.ieee.org/document/7206539
UR - http://www.scopus.com/inward/record.url?scp=84962329130&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2015.2469072
DO - 10.1109/TCSII.2015.2469072
M3 - Article
SN - 1549-7747
VL - 63
SP - 59
EP - 63
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 1
ER -