TY - JOUR
T1 - Design and VLSI implementation for a WCDMA multipath searcher
AU - Grayver, Eugene
AU - Frigon, Jean François
AU - Eltawil, Ahmed M.
AU - Tarighat, Alireza
AU - Shoarinejad, Kambiz
AU - Abbasfar, Aliazam
AU - Čabrić, Danijela
AU - Daneshrad, Babak
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2005/5/1
Y1 - 2005/5/1
N2 - The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 μm CMOS technology and requires only 150 k gates for a total area of 1.5 mm2 consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator. © 2005 IEEE.
AB - The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 μm CMOS technology and requires only 150 k gates for a total area of 1.5 mm2 consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator. © 2005 IEEE.
UR - http://ieeexplore.ieee.org/document/1433235/
UR - http://www.scopus.com/inward/record.url?scp=21244470760&partnerID=8YFLogxK
U2 - 10.1109/TVT.2005.844664
DO - 10.1109/TVT.2005.844664
M3 - Article
SN - 0018-9545
VL - 54
JO - IEEE Transactions on Vehicular Technology
JF - IEEE Transactions on Vehicular Technology
IS - 3
ER -