Design of CMOS-memristor Circuits for LSTM architecture

Kamilya Smagulova; Kazybek Adam; Olga Krestinskaya; Alex Pappachen James

doi:10.1109/EDSSC.2018.8487179

Design of CMOS-memristor Circuits for LSTM architecture

Kamilya Smagulova, Kazybek Adam, Olga Krestinskaya, Alex Pappachen James

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 μ m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.

Original language	English (US)
Title of host publication	2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781538662342
DOIs	https://doi.org/10.1109/EDSSC.2018.8487179
State	Published - Oct 9 2018
Externally published	Yes

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10.1109/EDSSC.2018.8487179

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title = "Design of CMOS-memristor Circuits for LSTM architecture",

abstract = "Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 μ m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.",

author = "Kamilya Smagulova and Kazybek Adam and Olga Krestinskaya and James, {Alex Pappachen}",

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AU - Adam, Kazybek

AU - Krestinskaya, Olga

AU - James, Alex Pappachen

N1 - Generated from Scopus record by KAUST IRTS on 2023-09-23

PY - 2018/10/9

Y1 - 2018/10/9

N2 - Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 μ m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.

AB - Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 μ m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.

UR - https://ieeexplore.ieee.org/document/8487179/

UR - http://www.scopus.com/inward/record.url?scp=85056326459&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2018.8487179

DO - 10.1109/EDSSC.2018.8487179

M3 - Conference contribution

SN - 9781538662342

BT - 2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Design of CMOS-memristor Circuits for LSTM architecture

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