Development of barrier slurry for improved electrical performance

As device dimensions shrink to the sub-65 nm regime, a greater demand is placed upon the barrier polishing process. Therefore the ability to modulate the barrier chemical mechanical planarization performance window by process and formulation synergy can provide tunability at advanced technology nodes to meet stringent electrical, topography, and defect requirements. This study introduces one approach in achieving the synergy between barrier polishing slurry and the development of a robust process. The system investigated has demonstrated desirable R_s uniformity control and greater margin for polishing. Extensive M_x layer testing (more than 10 wafer lots) has consistently shown better within-wafer R_s (resistance) spread compared to process of record, with improvement above 30% for all layers. The slurry also shows a more gradual R_s fluctuation over a 20 s polish time range. A marathon run has also shown consistent polishing rate performance over the pad life with comparable defect density and characteristics.