Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application

J. Huang; P. D. Kirsch; D. Heh; C. Y. Kang; G. Bersuker; M. Hussain; P. Majhi; P. Sivasubramani; D. C. Gilmer; N. Goel; M. A. Quevedo-Lopez; C. Young; C. S. Park; C. Park; P. Y. Hung; J. Price; H. R. Harris; B. H. Lee; H. H. Tseng; R. Jammy

doi:10.1109/IEDM.2008.4796609

Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application

J. Huang^*, P. D. Kirsch, D. Heh, C. Y. Kang, G. Bersuker, M. Hussain, P. Majhi, P. Sivasubramani, D. C. Gilmer, N. Goel, M. A. Quevedo-Lopez, C. Young, C. S. Park, C. Park, P. Y. Hung, J. Price, H. R. Harris, B. H. Lee, H. H. Tseng, R. Jammy

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V_t, as well as strongly affects mobility, N_it and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V_t tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO₂) IL. T_inv=1.15nm and V_t,lin=0.31V was obtained while achieving the following attributes: mobility∼70%, N _it <5×10¹⁰ cm^-2, δV _t<30mV within wafer, BTI δV_t <40mV at 125o°C. By optimizing these gate stack factors, we have developed and demonstrated structures for 22nm node LOP application. P. D. Kirsch.

Original language	English (US)
Title of host publication	2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs	https://doi.org/10.1109/IEDM.2008.4796609
State	Published - 2008
Externally published	Yes
Event	2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States Duration: Dec 15 2008 → Dec 17 2008

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2008 IEEE International Electron Devices Meeting, IEDM 2008
Country/Territory	United States
City	San Francisco, CA
Period	12/15/08 → 12/17/08

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2008.4796609

Cite this

Huang, J., Kirsch, P. D., Heh, D., Kang, C. Y., Bersuker, G., Hussain, M., Majhi, P., Sivasubramani, P., Gilmer, D. C., Goel, N., Quevedo-Lopez, M. A., Young, C., Park, C. S., Park, C., Hung, P. Y., Price, J., Harris, H. R., Lee, B. H., Tseng, H. H., & Jammy, R. (2008). Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application. In 2008 IEEE International Electron Devices Meeting, IEDM 2008 Article 4796609 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2008.4796609

@inproceedings{7fc6e1964e7b4f11850bb0a92967608c,

title = "Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application",

abstract = "For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls Vt, as well as strongly affects mobility, Nit and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved Vt tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO2) IL. Tinv=1.15nm and Vt,lin=0.31V was obtained while achieving the following attributes: mobility∼70%, N it <5×1010 cm-2, δV t<30mV within wafer, BTI δVt <40mV at 125o°C. By optimizing these gate stack factors, we have developed and demonstrated structures for 22nm node LOP application. P. D. Kirsch.",

author = "J. Huang and Kirsch, {P. D.} and D. Heh and Kang, {C. Y.} and G. Bersuker and M. Hussain and P. Majhi and P. Sivasubramani and Gilmer, {D. C.} and N. Goel and Quevedo-Lopez, {M. A.} and C. Young and Park, {C. S.} and C. Park and Hung, {P. Y.} and J. Price and Harris, {H. R.} and Lee, {B. H.} and Tseng, {H. H.} and R. Jammy",

year = "2008",

doi = "10.1109/IEDM.2008.4796609",

language = "English (US)",

isbn = "9781424423781",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

booktitle = "2008 IEEE International Electron Devices Meeting, IEDM 2008",

note = "2008 IEEE International Electron Devices Meeting, IEDM 2008 ; Conference date: 15-12-2008 Through 17-12-2008",

}

Huang, J, Kirsch, PD, Heh, D, Kang, CY, Bersuker, G, Hussain, M, Majhi, P, Sivasubramani, P, Gilmer, DC, Goel, N, Quevedo-Lopez, MA, Young, C, Park, CS, Park, C, Hung, PY, Price, J, Harris, HR, Lee, BH, Tseng, HH & Jammy, R 2008, Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application. in 2008 IEEE International Electron Devices Meeting, IEDM 2008., 4796609, Technical Digest - International Electron Devices Meeting, IEDM, 2008 IEEE International Electron Devices Meeting, IEDM 2008, San Francisco, CA, United States, 12/15/08. https://doi.org/10.1109/IEDM.2008.4796609

Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application. / Huang, J.; Kirsch, P. D.; Heh, D. et al.
2008 IEEE International Electron Devices Meeting, IEDM 2008. 2008. 4796609 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application

AU - Huang, J.

AU - Kirsch, P. D.

AU - Heh, D.

AU - Kang, C. Y.

AU - Bersuker, G.

AU - Hussain, M.

AU - Majhi, P.

AU - Sivasubramani, P.

AU - Gilmer, D. C.

AU - Goel, N.

AU - Quevedo-Lopez, M. A.

AU - Young, C.

AU - Park, C. S.

AU - Park, C.

AU - Hung, P. Y.

AU - Price, J.

AU - Harris, H. R.

AU - Lee, B. H.

AU - Tseng, H. H.

AU - Jammy, R.

PY - 2008

Y1 - 2008

N2 - For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls Vt, as well as strongly affects mobility, Nit and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved Vt tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO2) IL. Tinv=1.15nm and Vt,lin=0.31V was obtained while achieving the following attributes: mobility∼70%, N it <5×1010 cm-2, δV t<30mV within wafer, BTI δVt <40mV at 125o°C. By optimizing these gate stack factors, we have developed and demonstrated structures for 22nm node LOP application. P. D. Kirsch.

AB - For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls Vt, as well as strongly affects mobility, Nit and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved Vt tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO2) IL. Tinv=1.15nm and Vt,lin=0.31V was obtained while achieving the following attributes: mobility∼70%, N it <5×1010 cm-2, δV t<30mV within wafer, BTI δVt <40mV at 125o°C. By optimizing these gate stack factors, we have developed and demonstrated structures for 22nm node LOP application. P. D. Kirsch.

UR - http://www.scopus.com/inward/record.url?scp=64549153962&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2008.4796609

DO - 10.1109/IEDM.2008.4796609

M3 - Conference contribution

AN - SCOPUS:64549153962

SN - 9781424423781

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2008 IEEE International Electron Devices Meeting, IEDM 2008

T2 - 2008 IEEE International Electron Devices Meeting, IEDM 2008

Y2 - 15 December 2008 through 17 December 2008

ER -

Device and reliability improvement of HfSiON+LaOx/Metal gate stacks for 22nm node application

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