Dipole model explaining high-k/metal gate threshold voltage tuning

P. D. Kirsch; P. Sivasubramani; J. Huang; C. D. Young; C. S. Park; K. Freeman; M. M. Hussain; G. Bersuker; H. R. Harris; P. Majhi; P. Lysaght; H. H. Tseng; B. H. Lee; R. Jammy

doi:10.1149/1.3118953

Dipole model explaining high-k/metal gate threshold voltage tuning

P. D. Kirsch, P. Sivasubramani, J. Huang, C. D. Young, C. S. Park, K. Freeman, M. M. Hussain, G. Bersuker, H. R. Harris, P. Majhi, P. Lysaght, H. H. Tseng, B. H. Lee, R. Jammy

Computer, Electrical and Mathematical Sciences and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An interface dipole model explaining threshold voltage (V_t) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. The magnitude of nFET Vt tuning tuning depends on rare earth (RE) type and diffusion in Si/SiO_x/HfSiON/REOx cap layer/metal gated nFETs as follows: Sr < Er <Sc+Er < La < Sc < no cap layer. This V _t ordering is very similar to the trends in dopant electronegativity (EN, dipole charge transfer) and ionic radius (r, dipole separation) expected for a interfacial dipole mechanism. The resulting V_t dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

Original language	English (US)
Title of host publication	ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5
Subtitle of host publication	New Materials, Processes, and Equipment
Publisher	Electrochemical Society Inc.
Pages	269-276
Number of pages	8
Edition	1
ISBN (Electronic)	9781607680598
ISBN (Print)	9781566777094
DOIs	https://doi.org/10.1149/1.3118953
State	Published - 2009
Event	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting - San Francisco, CA, United States Duration: May 24 2009 → May 29 2009

Publication series

Name	ECS Transactions
Number	1
Volume	19
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Other

Other	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting
Country/Territory	United States
City	San Francisco, CA
Period	05/24/09 → 05/29/09

ASJC Scopus subject areas

General Engineering

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10.1149/1.3118953

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Kirsch, P. D., Sivasubramani, P., Huang, J., Young, C. D., Park, C. S., Freeman, K., Hussain, M. M., Bersuker, G., Harris, H. R., Majhi, P., Lysaght, P., Tseng, H. H., Lee, B. H., & Jammy, R. (2009). Dipole model explaining high-k/metal gate threshold voltage tuning. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment (1 ed., pp. 269-276). (ECS Transactions; Vol. 19, No. 1). Electrochemical Society Inc.. https://doi.org/10.1149/1.3118953

@inproceedings{79870b33011b4c00ba105249a6cb4d24,

title = "Dipole model explaining high-k/metal gate threshold voltage tuning",

abstract = "An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. The magnitude of nFET Vt tuning tuning depends on rare earth (RE) type and diffusion in Si/SiOx/HfSiON/REOx cap layer/metal gated nFETs as follows: Sr < Er t ordering is very similar to the trends in dopant electronegativity (EN, dipole charge transfer) and ionic radius (r, dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).",

author = "Kirsch, {P. D.} and P. Sivasubramani and J. Huang and Young, {C. D.} and Park, {C. S.} and K. Freeman and Hussain, {M. M.} and G. Bersuker and Harris, {H. R.} and P. Majhi and P. Lysaght and Tseng, {H. H.} and Lee, {B. H.} and R. Jammy",

year = "2009",

doi = "10.1149/1.3118953",

language = "English (US)",

isbn = "9781566777094",

series = "ECS Transactions",

publisher = "Electrochemical Society Inc.",

number = "1",

pages = "269--276",

booktitle = "ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5",

edition = "1",

note = "International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting ; Conference date: 24-05-2009 Through 29-05-2009",

}

Kirsch, PD, Sivasubramani, P, Huang, J, Young, CD, Park, CS, Freeman, K, Hussain, MM, Bersuker, G, Harris, HR, Majhi, P, Lysaght, P, Tseng, HH, Lee, BH & Jammy, R 2009, Dipole model explaining high-k/metal gate threshold voltage tuning. in ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment. 1 edn, ECS Transactions, no. 1, vol. 19, Electrochemical Society Inc., pp. 269-276, International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting, San Francisco, CA, United States, 05/24/09. https://doi.org/10.1149/1.3118953

Dipole model explaining high-k/metal gate threshold voltage tuning. / Kirsch, P. D.; Sivasubramani, P.; Huang, J. et al.
ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment. 1. ed. Electrochemical Society Inc., 2009. p. 269-276 (ECS Transactions; Vol. 19, No. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Dipole model explaining high-k/metal gate threshold voltage tuning

AU - Kirsch, P. D.

AU - Sivasubramani, P.

AU - Huang, J.

AU - Young, C. D.

AU - Park, C. S.

AU - Freeman, K.

AU - Hussain, M. M.

AU - Bersuker, G.

AU - Harris, H. R.

AU - Majhi, P.

AU - Lysaght, P.

AU - Tseng, H. H.

AU - Lee, B. H.

AU - Jammy, R.

PY - 2009

Y1 - 2009

N2 - An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. The magnitude of nFET Vt tuning tuning depends on rare earth (RE) type and diffusion in Si/SiOx/HfSiON/REOx cap layer/metal gated nFETs as follows: Sr < Er t ordering is very similar to the trends in dopant electronegativity (EN, dipole charge transfer) and ionic radius (r, dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

AB - An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. The magnitude of nFET Vt tuning tuning depends on rare earth (RE) type and diffusion in Si/SiOx/HfSiON/REOx cap layer/metal gated nFETs as follows: Sr < Er t ordering is very similar to the trends in dopant electronegativity (EN, dipole charge transfer) and ionic radius (r, dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

UR - http://www.scopus.com/inward/record.url?scp=74949110633&partnerID=8YFLogxK

U2 - 10.1149/1.3118953

DO - 10.1149/1.3118953

M3 - Conference contribution

AN - SCOPUS:74949110633

SN - 9781566777094

T3 - ECS Transactions

SP - 269

EP - 276

BT - ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5

PB - Electrochemical Society Inc.

T2 - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting

Y2 - 24 May 2009 through 29 May 2009

ER -

Kirsch PD, Sivasubramani P, Huang J, Young CD, Park CS, Freeman K et al. Dipole model explaining high-k/metal gate threshold voltage tuning. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment. 1 ed. Electrochemical Society Inc. 2009. p. 269-276. (ECS Transactions; 1). doi: 10.1149/1.3118953

Dipole model explaining high-k/metal gate threshold voltage tuning

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