Skip to main navigation
Skip to search
Skip to main content
KAUST FACULTY PORTAL Home
Home
Profiles
Research units
Research output
Prizes
Courses
Equipment
Student theses
Datasets
Press/Media
Search by expertise, name or affiliation
Dynamic voltage scaling continuous adaptive-size cell design technique
Sami Kirolos, Yehia Massoud
Research output
:
Contribution to journal
›
Article
›
peer-review
1
Scopus citations
Overview
Fingerprint
Fingerprint
Dive into the research topics of 'Dynamic voltage scaling continuous adaptive-size cell design technique'. Together they form a unique fingerprint.
Sort by
Weight
Alphabetically
Keyphrases
Supply Voltage
100%
Dynamic Voltage Scaling
100%
Cell Design
100%
Design Techniques
100%
Adaptive Size
100%
High Performance
66%
Size Ratio
66%
Subthreshold Region
66%
Circuit Design
33%
Logic Gates
33%
Ring Oscillator
33%
Power Dissipation
33%
Propagation Delay
33%
Combinational Logic
33%
Noise Margin
33%
Pullout
33%
Effective Size
33%
Gate Size
33%
Minimum Power
33%
PMOS Transistor
33%
Voltage Transfer Characteristics
33%
Subthreshold Operation
33%
Balanced Operation
33%
Scaling Scheme
33%
Energy-related Operations
33%
Minimum Energy Operation
33%
Adaptive Learning Rate
33%
Size Design
33%
Power Propagation
33%
Engineering
Design Technique
100%
Voltage Scaling
100%
Cell Design
100%
Supply Voltage
100%
Simulation Result
33%
Circuit Design
33%
Energy Dissipation
33%
Effective Size
33%
Logic Gate
33%
Propagation Delay
33%
Noise Margin
33%
Computer Science
Supply Voltage
100%
Dynamic Voltage Scaling
100%
Design Technique
100%
Logic Gate
33%
Ring Oscillator
33%
Power Dissipation
33%
Propagation Delay
33%
Combinational Logic
33%
Noise Margin
33%
Transfer Characteristic
33%