Efficient overlay architecture based on DSP blocks

Abhishek Kumar Jain; Suhaib A. Fahmy; Douglas L. Maskell

doi:10.1109/FCCM.2015.15

Efficient overlay architecture based on DSP blocks

Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

36 Scopus citations

Abstract

Design productivity and long compilation times are major issues preventing the mainstream adoption of FPGAs in general purpose computing. Several overlay architectures have emerged to tackle these challenges, but at the cost of increased area and performance overheads. This paper examines a coarse grained overlay architecture designed using the flexible DSP48E1 primitive on Xilinx FPGAs. This allows pipelined execution at significantly higher throughput without adding significant area overheads to the PE. We map several benchmarks, using our custom mapping tool, and show that the proposed overlay architecture delivers a throughput of up to 21.6 GOPS and provides an 11 - 52% improvement in throughput compared to Vivado HLS implementations.

Original language	English (US)
Title of host publication	Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	25-28
Number of pages	4
ISBN (Print)	9781479999699
DOIs	https://doi.org/10.1109/FCCM.2015.15
State	Published - Jan 1 2015
Externally published	Yes

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10.1109/FCCM.2015.15

Cite this

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title = "Efficient overlay architecture based on DSP blocks",

abstract = "Design productivity and long compilation times are major issues preventing the mainstream adoption of FPGAs in general purpose computing. Several overlay architectures have emerged to tackle these challenges, but at the cost of increased area and performance overheads. This paper examines a coarse grained overlay architecture designed using the flexible DSP48E1 primitive on Xilinx FPGAs. This allows pipelined execution at significantly higher throughput without adding significant area overheads to the PE. We map several benchmarks, using our custom mapping tool, and show that the proposed overlay architecture delivers a throughput of up to 21.6 GOPS and provides an 11 - 52% improvement in throughput compared to Vivado HLS implementations.",

author = "Jain, {Abhishek Kumar} and Fahmy, {Suhaib A.} and Maskell, {Douglas L.}",

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Efficient overlay architecture based on DSP blocks. / Jain, Abhishek Kumar; Fahmy, Suhaib A.; Maskell, Douglas L.
Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 25-28.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Design productivity and long compilation times are major issues preventing the mainstream adoption of FPGAs in general purpose computing. Several overlay architectures have emerged to tackle these challenges, but at the cost of increased area and performance overheads. This paper examines a coarse grained overlay architecture designed using the flexible DSP48E1 primitive on Xilinx FPGAs. This allows pipelined execution at significantly higher throughput without adding significant area overheads to the PE. We map several benchmarks, using our custom mapping tool, and show that the proposed overlay architecture delivers a throughput of up to 21.6 GOPS and provides an 11 - 52% improvement in throughput compared to Vivado HLS implementations.

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BT - Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Efficient overlay architecture based on DSP blocks

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