Abstract
In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%. © 2007 IEEE.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 897-900 |
Number of pages | 4 |
DOIs | |
State | Published - Jan 1 2007 |
Externally published | Yes |