TY - GEN
T1 - Evaluating the efficiency of DSP Block synthesis inference from flow graphs
AU - Ronak, Bajaj
AU - Fahmy, Suhaib A.
N1 - Generated from Scopus record by KAUST IRTS on 2021-03-16
PY - 2012/12/12
Y1 - 2012/12/12
N2 - The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation. © 2012 IEEE.
AB - The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation. © 2012 IEEE.
UR - http://ieeexplore.ieee.org/document/6339163/
UR - http://www.scopus.com/inward/record.url?scp=84870697384&partnerID=8YFLogxK
U2 - 10.1109/FPL.2012.6339163
DO - 10.1109/FPL.2012.6339163
M3 - Conference contribution
SN - 9781467322560
SP - 727
EP - 730
BT - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
ER -