Evaluating the efficiency of DSP Block synthesis inference from flow graphs

Bajaj Ronak, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations


The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation. © 2012 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Number of pages4
StatePublished - Dec 12 2012
Externally publishedYes


Dive into the research topics of 'Evaluating the efficiency of DSP Block synthesis inference from flow graphs'. Together they form a unique fingerprint.

Cite this