Multi-core processors pervade numerous industries but they still represent a challenge for the aerospace industry, where strong certification of every components is required. One way to make them enforce safety-criticality constraints is to ensure reallocation of critical tasks on the chip when they are affected by hardware faults. This paper describes and compares different models of a task reallocation problem for a reconfigurable multi-core architecture. It also presents the first version of the macroscopic model made of Raspberry Pi that was built to represent the multi-core architecture and to test the task allocation algorithm on an actual system, showing the increased robustness that the reallocation algorithm enables while cores are made faulty.
|Original language||English (US)|
|Title of host publication||AIAA/IEEE Digital Avionics Systems Conference - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Dec 7 2018|