Experimental verification of on-chip CMOS fractional-order capacitor emulators

G. Tsirimokou; C. Psychalinos; Khaled N. Salama; A.S. Elwakil

doi:10.1049/el.2016.1457

Experimental verification of on-chip CMOS fractional-order capacitor emulators

G. Tsirimokou, C. Psychalinos, Khaled N. Salama, A.S. Elwakil

King Abdullah University of Science and Technology

Research output: Contribution to journal › Article › peer-review

61 Scopus citations

Abstract

The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

Original language	English (US)
Pages (from-to)	1298-1300
Number of pages	3
Journal	Electronics Letters
Volume	52
Issue number	15
DOIs	https://doi.org/10.1049/el.2016.1457
State	Published - Jun 13 2016

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10.1049/el.2016.1457

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@article{056c8425dc444399b90c0b9971c43fa7,

title = "Experimental verification of on-chip CMOS fractional-order capacitor emulators",

abstract = "The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. {\textcopyright} 2016 The Institution of Engineering and Technology.",

author = "G. Tsirimokou and C. Psychalinos and Salama, {Khaled N.} and A.S. Elwakil",

note = "KAUST Repository Item: Exported on 2020-10-01",

year = "2016",

month = jun,

day = "13",

doi = "10.1049/el.2016.1457",

language = "English (US)",

volume = "52",

pages = "1298--1300",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "15",

}

TY - JOUR

T1 - Experimental verification of on-chip CMOS fractional-order capacitor emulators

AU - Tsirimokou, G.

AU - Psychalinos, C.

AU - Salama, Khaled N.

AU - Elwakil, A.S.

N1 - KAUST Repository Item: Exported on 2020-10-01

PY - 2016/6/13

Y1 - 2016/6/13

N2 - The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

AB - The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

UR - http://hdl.handle.net/10754/621648

UR - http://www.crossref.org/iPage?doi=10.1049%2Fel.2016.1457

UR - http://www.scopus.com/inward/record.url?scp=84978665424&partnerID=8YFLogxK

U2 - 10.1049/el.2016.1457

DO - 10.1049/el.2016.1457

M3 - Article

SN - 0013-5194

VL - 52

SP - 1298

EP - 1300

JO - Electronics Letters

JF - Electronics Letters

IS - 15

ER -

Experimental verification of on-chip CMOS fractional-order capacitor emulators

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