TY - JOUR
T1 - Exploiting Smallest Error to Calibrate Non-linearity in SAR ADCs
AU - Fan, Hua
AU - Li, Jingtao
AU - Feng, Quanyuan
AU - Diao, Xiaopeng
AU - Lin, Lishuang
AU - Zhang, Kelin
AU - Sun, Haiding
AU - Heidari, Hadi
N1 - KAUST Repository Item: Exported on 2020-10-01
Acknowledgements: The work of Hua Fan was supported by the National Natural Science Foundation of China (NSFC) under Grant 61771111, as well as supported by China Postdoctoral Science Foundation under grant 2017M612940 and Special Foundation of Sichuan Provincial Postdoctoral Science Foundation. The work of Quanyuan Feng was supported by the National Natural Science Foundation of China (NSFC) under Grant 61531016, supported by the project of Science and Technology Support Program of Sichuan Province under Grant 2018GZ0139, and in part by the Sichuan Provincial Science and Technology Important Projects under Grant 2017GZ0110.
PY - 2018/7/3
Y1 - 2018/7/3
N2 - This paper presents a statistics-optimised organisation technique to achieve better element matching in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in smart sensor systems. We demonstrate the proposed technique ability to achieve a significant improvement of around 23 dB on Spurious Free Dynamic Range (SFDR) of the ADC than the conventional, testing with a capacitor mismatch σu = 0.2% in a 14 bit SAR ADC system. For the static performance, the max root mean square (rms) value of differential nonlinearity (DNL) reduces from 1.63 to 0.20 LSB and the max rms value of integral nonlinearity (INL) reduces from 2.10 to 0.21 LSB. In addition, it is demonstrated that by applying grouping optimisation and strategy optimisation, the performance boosting on SFDR can be effectively achieved. Such great improvement on the resolution of the ADC only requires an off-line pre-processing digital part.
AB - This paper presents a statistics-optimised organisation technique to achieve better element matching in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in smart sensor systems. We demonstrate the proposed technique ability to achieve a significant improvement of around 23 dB on Spurious Free Dynamic Range (SFDR) of the ADC than the conventional, testing with a capacitor mismatch σu = 0.2% in a 14 bit SAR ADC system. For the static performance, the max root mean square (rms) value of differential nonlinearity (DNL) reduces from 1.63 to 0.20 LSB and the max rms value of integral nonlinearity (INL) reduces from 2.10 to 0.21 LSB. In addition, it is demonstrated that by applying grouping optimisation and strategy optimisation, the performance boosting on SFDR can be effectively achieved. Such great improvement on the resolution of the ADC only requires an off-line pre-processing digital part.
UR - http://hdl.handle.net/10754/628363
UR - https://ieeexplore.ieee.org/document/8402222/
UR - http://www.scopus.com/inward/record.url?scp=85049457585&partnerID=8YFLogxK
U2 - 10.1109/ACCESS.2018.2852729
DO - 10.1109/ACCESS.2018.2852729
M3 - Article
SN - 2169-3536
VL - 6
SP - 42930
EP - 42940
JO - IEEE Access
JF - IEEE Access
ER -