Fast error aware model for arithmetic and logic circuits

Samy Zaynoun; Muhammad S. Khairy; Ahmed M. Eltawil; Fadi J. Kurdahi; Amin Khajeh

doi:10.1109/ICCD.2012.6378659

Fast error aware model for arithmetic and logic circuits

Samy Zaynoun, Muhammad S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi, Amin Khajeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Scopus citations

Abstract

As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability. © 2012 IEEE.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOIs	https://doi.org/10.1109/ICCD.2012.6378659
State	Published - Dec 1 2012
Externally published	Yes

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10.1109/ICCD.2012.6378659

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title = "Fast error aware model for arithmetic and logic circuits",

abstract = "As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability. {\textcopyright} 2012 IEEE.",

author = "Samy Zaynoun and Khairy, {Muhammad S.} and Eltawil, {Ahmed M.} and Kurdahi, {Fadi J.} and Amin Khajeh",

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AU - Khairy, Muhammad S.

AU - Eltawil, Ahmed M.

AU - Kurdahi, Fadi J.

AU - Khajeh, Amin

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2012/12/1

Y1 - 2012/12/1

N2 - As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability. © 2012 IEEE.

AB - As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability. © 2012 IEEE.

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U2 - 10.1109/ICCD.2012.6378659

DO - 10.1109/ICCD.2012.6378659

M3 - Conference contribution

SN - 9781467330503

BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

ER -

Fast error aware model for arithmetic and logic circuits

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