Gate dielectrics for high performance and low power CMOS SoC applications

F. Cubaynes; C. Dachs; C. Detcheverry; A. Zegers; V. Venezia; J. Schmitz; P. Stolk; M. Jurczak; K. Henson; R. Degraeve; A. Rothschild; T. Conard; J. Petry; M. Da Rold; M. Schaekers; G. Badenes; L. Date; D. Pique; H. Al-Shareef; R. Murto

doi:10.1109/ESSDERC.2002.194959

Gate dielectrics for high performance and low power CMOS SoC applications

F. Cubaynes^*, C. Dachs, C. Detcheverry, A. Zegers, V. Venezia, J. Schmitz, P. Stolk, M. Jurczak, K. Henson, R. Degraeve, A. Rothschild, T. Conard, J. Petry, M. Da Rold, M. Schaekers, G. Badenes, L. Date, D. Pique, H. Al-Shareef, R. Murto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.

Original language	English (US)
Title of host publication	European Solid-State Device Research Conference
Editors	Elena Gnani, Giorgio Baccarani, Massimo Rudan
Publisher	IEEE Computer Society
Pages	427-430
Number of pages	4
ISBN (Electronic)	8890084782
DOIs	https://doi.org/10.1109/ESSDERC.2002.194959
State	Published - 2002
Externally published	Yes
Event	32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy Duration: Sep 24 2002 → Sep 26 2002

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Other

Other	32nd European Solid-State Device Research Conference, ESSDERC 2002
Country/Territory	Italy
City	Firenze
Period	09/24/02 → 09/26/02

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ESSDERC.2002.194959

Cite this

Cubaynes, F., Dachs, C., Detcheverry, C., Zegers, A., Venezia, V., Schmitz, J., Stolk, P., Jurczak, M., Henson, K., Degraeve, R., Rothschild, A., Conard, T., Petry, J., Da Rold, M., Schaekers, M., Badenes, G., Date, L., Pique, D., Al-Shareef, H., & Murto, R. (2002). Gate dielectrics for high performance and low power CMOS SoC applications. In E. Gnani, G. Baccarani, & M. Rudan (Eds.), European Solid-State Device Research Conference (pp. 427-430). (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2002.194959

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title = "Gate dielectrics for high performance and low power CMOS SoC applications",

abstract = "This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.",

author = "F. Cubaynes and C. Dachs and C. Detcheverry and A. Zegers and V. Venezia and J. Schmitz and P. Stolk and M. Jurczak and K. Henson and R. Degraeve and A. Rothschild and T. Conard and J. Petry and {Da Rold}, M. and M. Schaekers and G. Badenes and L. Date and D. Pique and H. Al-Shareef and R. Murto",

year = "2002",

doi = "10.1109/ESSDERC.2002.194959",

language = "English (US)",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "427--430",

editor = "Elena Gnani and Giorgio Baccarani and Massimo Rudan",

booktitle = "European Solid-State Device Research Conference",

address = "United States",

note = "32nd European Solid-State Device Research Conference, ESSDERC 2002 ; Conference date: 24-09-2002 Through 26-09-2002",

}

Cubaynes, F, Dachs, C, Detcheverry, C, Zegers, A, Venezia, V, Schmitz, J, Stolk, P, Jurczak, M, Henson, K, Degraeve, R, Rothschild, A, Conard, T, Petry, J, Da Rold, M, Schaekers, M, Badenes, G, Date, L, Pique, D, Al-Shareef, H & Murto, R 2002, Gate dielectrics for high performance and low power CMOS SoC applications. in E Gnani, G Baccarani & M Rudan (eds), European Solid-State Device Research Conference. European Solid-State Device Research Conference, IEEE Computer Society, pp. 427-430, 32nd European Solid-State Device Research Conference, ESSDERC 2002, Firenze, Italy, 09/24/02. https://doi.org/10.1109/ESSDERC.2002.194959

Gate dielectrics for high performance and low power CMOS SoC applications. / Cubaynes, F.; Dachs, C.; Detcheverry, C. et al.
European Solid-State Device Research Conference. ed. / Elena Gnani; Giorgio Baccarani; Massimo Rudan. IEEE Computer Society, 2002. p. 427-430 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Gate dielectrics for high performance and low power CMOS SoC applications

AU - Cubaynes, F.

AU - Dachs, C.

AU - Detcheverry, C.

AU - Zegers, A.

AU - Venezia, V.

AU - Schmitz, J.

AU - Stolk, P.

AU - Jurczak, M.

AU - Henson, K.

AU - Degraeve, R.

AU - Rothschild, A.

AU - Conard, T.

AU - Petry, J.

AU - Da Rold, M.

AU - Schaekers, M.

AU - Badenes, G.

AU - Date, L.

AU - Pique, D.

AU - Al-Shareef, H.

AU - Murto, R.

PY - 2002

Y1 - 2002

N2 - This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.

AB - This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.

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M3 - Conference contribution

AN - SCOPUS:84907702334

T3 - European Solid-State Device Research Conference

SP - 427

EP - 430

BT - European Solid-State Device Research Conference

A2 - Gnani, Elena

A2 - Baccarani, Giorgio

A2 - Rudan, Massimo

PB - IEEE Computer Society

T2 - 32nd European Solid-State Device Research Conference, ESSDERC 2002

Y2 - 24 September 2002 through 26 September 2002

ER -

Gate dielectrics for high performance and low power CMOS SoC applications

Abstract

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