Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application

J. Huang*, D. Heh, P. Sivasubramani, P. D. Kirsch, G. Bersuker, D. C. Gilmer, M. A. Quevedo-Lopez, M. M. Hussain, P. Majhi, P. Lysaght, H. Park, N. Goel, C. Young, C. S. Park, C. Park, M. Cruz, V. Diaz, P. Y. Hung, J. Price, H. H. TsengR. Jammy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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