TY - GEN
T1 - Hardware Acceleration of DNA Pattern Matching with Binary Memristors
AU - Bazzi, Jinane
AU - Fouda, Mohammed E.
AU - Kanj, Rouwaida
AU - Eltawil, Ahmed
N1 - KAUST Repository Item: Exported on 2023-07-24
PY - 2023/7/21
Y1 - 2023/7/21
N2 - DNA pattern matching is a key technique applied in many bioinformatics applications. Recently, this technique has become very popular and is widely used for genetic disease diagnosis, where finding the number of consecutive repeats of a specific DNA pattern indicates the type and intensity of the patient's disorder. However, the remarkable growth of DNA data exacerbates the latency and power consumption required to perform DNA pattern matching. In this work, we propose a hardware accelerator design to detect the presence of different diseases efficiently using DNA pattern matching. We propose a novel CAM cell using binary memristors for reliable and robust data encoding. The proposed architecture consists of two main building blocks the Content-addressable memory (CAM) and pattern detector circuits in addition to the needed peripheral circuits for CAM read, write and match operation. CMOS PTM 45nm technology was used to design and simulate the full architecture. The evaluation of the proposed design shows ∼2× improvement in energy-delay-area product compared to the state-of-art work in the literature, in addition to robustness against noise and process variations.
AB - DNA pattern matching is a key technique applied in many bioinformatics applications. Recently, this technique has become very popular and is widely used for genetic disease diagnosis, where finding the number of consecutive repeats of a specific DNA pattern indicates the type and intensity of the patient's disorder. However, the remarkable growth of DNA data exacerbates the latency and power consumption required to perform DNA pattern matching. In this work, we propose a hardware accelerator design to detect the presence of different diseases efficiently using DNA pattern matching. We propose a novel CAM cell using binary memristors for reliable and robust data encoding. The proposed architecture consists of two main building blocks the Content-addressable memory (CAM) and pattern detector circuits in addition to the needed peripheral circuits for CAM read, write and match operation. CMOS PTM 45nm technology was used to design and simulate the full architecture. The evaluation of the proposed design shows ∼2× improvement in energy-delay-area product compared to the state-of-art work in the literature, in addition to robustness against noise and process variations.
UR - http://hdl.handle.net/10754/693185
UR - https://ieeexplore.ieee.org/document/10181367/
U2 - 10.1109/iscas46773.2023.10181367
DO - 10.1109/iscas46773.2023.10181367
M3 - Conference contribution
BT - 2023 IEEE International Symposium on Circuits and Systems (ISCAS)
PB - IEEE
ER -